| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr5.c | 24 #include "ram.h"
35 nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) in nvkm_gddr5_calc() argument
39 int rq = ram->freq < 1000000; /* XXX */ in nvkm_gddr5_calc()
41 xd = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr5_calc()
43 switch (ram->next->bios.ramcfg_ver) { in nvkm_gddr5_calc()
45 pd = ram->next->bios.ramcfg_11_01_80; in nvkm_gddr5_calc()
46 lf = ram->next->bios.ramcfg_11_01_40; in nvkm_gddr5_calc()
47 vh = ram->next->bios.ramcfg_11_02_10; in nvkm_gddr5_calc()
48 vr = ram->next->bios.ramcfg_11_02_04; in nvkm_gddr5_calc()
49 vo = ram->next->bios.ramcfg_11_06; in nvkm_gddr5_calc()
[all …]
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| D | ramgk104.c | 25 #include "ram.h"
143 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); in gk104_ram_train() local
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { in gk104_ram_train()
150 if (ram->pmask & (1 << i)) in gk104_ram_train()
159 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); in r1373f4_init() local
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in r1373f4_init()
162 const u32 runk0 = ram->fN1 << 16; in r1373f4_init()
163 const u32 runk1 = ram->fN1; in r1373f4_init()
165 if (ram->from == 2) { in r1373f4_init()
[all …]
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| D | ram.c | 25 #include "ram.h"
32 struct nvkm_ram *ram; member
84 mutex_lock(&vram->ram->fb->subdev.mutex); in nvkm_vram_dtor()
87 nvkm_mm_free(&vram->ram->vram, &node); in nvkm_vram_dtor()
89 mutex_unlock(&vram->ram->fb->subdev.mutex); in nvkm_vram_dtor()
107 struct nvkm_ram *ram; in nvkm_ram_get() local
117 if (!device->fb || !(ram = device->fb->ram)) in nvkm_ram_get()
119 ram = device->fb->ram; in nvkm_ram_get()
120 mm = &ram->vram; in nvkm_ram_get()
125 vram->ram = ram; in nvkm_ram_get()
[all …]
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| D | ramfuc.h | 59 ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb) in ramfuc_init() argument
61 int ret = nvkm_memx_init(fb->subdev.device->pmu, &ram->memx); in ramfuc_init()
65 ram->sequence++; in ramfuc_init()
66 ram->fb = fb; in ramfuc_init()
71 ramfuc_exec(struct ramfuc *ram, bool exec) in ramfuc_exec() argument
74 if (ram->fb) { in ramfuc_exec()
75 ret = nvkm_memx_fini(&ram->memx, exec); in ramfuc_exec()
76 ram->fb = NULL; in ramfuc_exec()
82 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) in ramfuc_rd32() argument
84 struct nvkm_device *device = ram->fb->subdev.device; in ramfuc_rd32()
[all …]
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| D | ramnv50.c | 25 #include "ram.h"
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
99 ram->base.next->bios.rammap_00_16_40) << 16 | in nv50_ram_timing_calc()
133 if (ram->base.type == NVKM_RAM_TYPE_DDR2) { in nv50_ram_timing_calc()
137 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { in nv50_ram_timing_calc()
151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_read() argument
[all …]
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| D | gddr3.c | 25 #include "ram.h"
71 nvkm_gddr3_calc(struct nvkm_ram *ram) in nvkm_gddr3_calc() argument
75 switch (ram->next->bios.timing_ver) { in nvkm_gddr3_calc()
77 CWL = ram->next->bios.timing_10_CWL; in nvkm_gddr3_calc()
78 CL = ram->next->bios.timing_10_CL; in nvkm_gddr3_calc()
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
81 ODT = ram->next->bios.timing_10_ODT; in nvkm_gddr3_calc()
82 RON = ram->next->bios.ramcfg_RON; in nvkm_gddr3_calc()
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr3_calc()
[all …]
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| D | ramgt215.c | 26 #include "ram.h"
154 gt215_link_train(struct gt215_ram *ram) in gt215_link_train() argument
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
157 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_link_train()
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
194 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); in gt215_link_train()
237 ram->base.func->calc(&ram->base, clk_current); in gt215_link_train()
246 ram_train_result(ram->base.fb, result, 64); in gt215_link_train()
272 gt215_link_train_init(struct gt215_ram *ram) in gt215_link_train_init() argument
280 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train_init()
[all …]
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| D | ramgf100.c | 25 #include "ram.h"
109 struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); in gf100_ram_train() local
110 struct nvkm_fb *fb = ram->base.fb; in gf100_ram_train()
129 struct gf100_ram *ram = gf100_ram(base); in gf100_ram_calc() local
130 struct gf100_ramfuc *fuc = &ram->fuc; in gf100_ram_calc()
131 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gf100_ram_calc()
180 ret = ram_init(fuc, ram->base.fb); in gf100_ram_calc()
215 ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk, in gf100_ram_calc()
230 ret = gt215_pll_calc(subdev, &ram->mempll, freq, in gf100_ram_calc()
409 struct gf100_ram *ram = gf100_ram(base); in gf100_ram_prog() local
[all …]
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| D | sddr3.c | 26 #include "ram.h"
70 nvkm_sddr3_calc(struct nvkm_ram *ram) in nvkm_sddr3_calc() argument
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
76 switch (ram->next->bios.timing_ver) { in nvkm_sddr3_calc()
78 if (ram->next->bios.timing_hdr < 0x17) { in nvkm_sddr3_calc()
82 CWL = ram->next->bios.timing_10_CWL; in nvkm_sddr3_calc()
83 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
85 ODT = ram->next->bios.timing_10_ODT; in nvkm_sddr3_calc()
88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_sddr3_calc()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr5.c | 24 #include "ram.h"
35 nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) in nvkm_gddr5_calc() argument
39 int rq = ram->freq < 1000000; /* XXX */ in nvkm_gddr5_calc()
41 xd = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr5_calc()
43 switch (ram->next->bios.ramcfg_ver) { in nvkm_gddr5_calc()
45 pd = ram->next->bios.ramcfg_11_01_80; in nvkm_gddr5_calc()
46 lf = ram->next->bios.ramcfg_11_01_40; in nvkm_gddr5_calc()
47 vh = ram->next->bios.ramcfg_11_02_10; in nvkm_gddr5_calc()
48 vr = ram->next->bios.ramcfg_11_02_04; in nvkm_gddr5_calc()
49 vo = ram->next->bios.ramcfg_11_06; in nvkm_gddr5_calc()
[all …]
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| D | ramgk104.c | 25 #include "ram.h"
143 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); in gk104_ram_train() local
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { in gk104_ram_train()
150 if (ram->pmask & (1 << i)) in gk104_ram_train()
159 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); in r1373f4_init() local
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in r1373f4_init()
162 const u32 runk0 = ram->fN1 << 16; in r1373f4_init()
163 const u32 runk1 = ram->fN1; in r1373f4_init()
165 if (ram->from == 2) { in r1373f4_init()
[all …]
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| D | ram.c | 25 #include "ram.h"
33 struct nvkm_ram *ram; member
41 return nvkm_instobj_wrap(nvkm_vram(memory)->ram->fb->subdev.device, memory, pmemory); in nvkm_vram_kmap()
91 mutex_lock(&vram->ram->mutex); in nvkm_vram_dtor()
94 nvkm_mm_free(&vram->ram->vram, &node); in nvkm_vram_dtor()
96 mutex_unlock(&vram->ram->mutex); in nvkm_vram_dtor()
115 struct nvkm_ram *ram; in nvkm_ram_get() local
125 if (!device->fb || !(ram = device->fb->ram)) in nvkm_ram_get()
127 ram = device->fb->ram; in nvkm_ram_get()
128 mm = &ram->vram; in nvkm_ram_get()
[all …]
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| D | ramfuc.h | 59 ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb) in ramfuc_init() argument
61 int ret = nvkm_memx_init(fb->subdev.device->pmu, &ram->memx); in ramfuc_init()
65 ram->sequence++; in ramfuc_init()
66 ram->fb = fb; in ramfuc_init()
71 ramfuc_exec(struct ramfuc *ram, bool exec) in ramfuc_exec() argument
74 if (ram->fb) { in ramfuc_exec()
75 ret = nvkm_memx_fini(&ram->memx, exec); in ramfuc_exec()
76 ram->fb = NULL; in ramfuc_exec()
82 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) in ramfuc_rd32() argument
84 struct nvkm_device *device = ram->fb->subdev.device; in ramfuc_rd32()
[all …]
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| D | ramnv50.c | 25 #include "ram.h"
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
99 ram->base.next->bios.rammap_00_16_40) << 16 | in nv50_ram_timing_calc()
133 if (ram->base.type == NVKM_RAM_TYPE_DDR2) { in nv50_ram_timing_calc()
137 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { in nv50_ram_timing_calc()
151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_read() argument
[all …]
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| D | gddr3.c | 25 #include "ram.h"
71 nvkm_gddr3_calc(struct nvkm_ram *ram) in nvkm_gddr3_calc() argument
75 switch (ram->next->bios.timing_ver) { in nvkm_gddr3_calc()
77 CWL = ram->next->bios.timing_10_CWL; in nvkm_gddr3_calc()
78 CL = ram->next->bios.timing_10_CL; in nvkm_gddr3_calc()
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
81 ODT = ram->next->bios.timing_10_ODT; in nvkm_gddr3_calc()
82 RON = ram->next->bios.ramcfg_RON; in nvkm_gddr3_calc()
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr3_calc()
[all …]
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| D | ramgt215.c | 26 #include "ram.h"
154 gt215_link_train(struct gt215_ram *ram) in gt215_link_train() argument
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
157 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_link_train()
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
194 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); in gt215_link_train()
237 ram->base.func->calc(&ram->base, clk_current); in gt215_link_train()
246 ram_train_result(ram->base.fb, result, 64); in gt215_link_train()
272 gt215_link_train_init(struct gt215_ram *ram) in gt215_link_train_init() argument
280 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train_init()
[all …]
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| D | ramgf100.c | 25 #include "ram.h"
109 struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); in gf100_ram_train() local
110 struct nvkm_fb *fb = ram->base.fb; in gf100_ram_train()
129 struct gf100_ram *ram = gf100_ram(base); in gf100_ram_calc() local
130 struct gf100_ramfuc *fuc = &ram->fuc; in gf100_ram_calc()
131 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gf100_ram_calc()
180 ret = ram_init(fuc, ram->base.fb); in gf100_ram_calc()
215 ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk, in gf100_ram_calc()
230 ret = gt215_pll_calc(subdev, &ram->mempll, freq, in gf100_ram_calc()
409 struct gf100_ram *ram = gf100_ram(base); in gf100_ram_prog() local
[all …]
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| D | sddr3.c | 26 #include "ram.h"
70 nvkm_sddr3_calc(struct nvkm_ram *ram) in nvkm_sddr3_calc() argument
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
76 switch (ram->next->bios.timing_ver) { in nvkm_sddr3_calc()
78 if (ram->next->bios.timing_hdr < 0x17) { in nvkm_sddr3_calc()
82 CWL = ram->next->bios.timing_10_CWL; in nvkm_sddr3_calc()
83 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
85 ODT = ram->next->bios.timing_10_ODT; in nvkm_sddr3_calc()
88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_sddr3_calc()
[all …]
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| /kernel/linux/linux-5.10/drivers/zorro/ |
| D | zorro.ids | 18 0000 Golem RAM Box 2MB [RAM Expansion]
22 1300 Warp Engine [Accelerator, SCSI Host Adapter and RAM Expansion]
24 0200 Megamix 2000 [RAM Expansion]
36 0a00 A590/A2052/A2058/A2091 [RAM Expansion]
37 2000 A560 [RAM Expansion]
40 5000 A2620 68020 [Accelerator and RAM Expansion]
41 5100 A2630 68030 [Accelerator and RAM Expansion]
51 0200 EXP8000 [RAM Expansion]
64 0100 AX2000 [RAM Expansion]
68 0000 StarBoard II [RAM Expansion]
[all …]
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| /kernel/linux/linux-6.6/drivers/zorro/ |
| D | zorro.ids | 18 0000 Golem RAM Box 2MB [RAM Expansion]
22 1300 Warp Engine [Accelerator, SCSI Host Adapter and RAM Expansion]
24 0200 Megamix 2000 [RAM Expansion]
36 0a00 A590/A2052/A2058/A2091 [RAM Expansion]
37 2000 A560 [RAM Expansion]
40 5000 A2620 68020 [Accelerator and RAM Expansion]
41 5100 A2630 68030 [Accelerator and RAM Expansion]
51 0200 EXP8000 [RAM Expansion]
64 0100 AX2000 [RAM Expansion]
68 0000 StarBoard II [RAM Expansion]
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bus/ |
| D | hwsq.h | 61 hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev) in hwsq_init() argument
65 ret = nvkm_hwsq_init(subdev, &ram->hwsq); in hwsq_init()
69 ram->sequence++; in hwsq_init()
70 ram->subdev = subdev; in hwsq_init()
75 hwsq_exec(struct hwsq *ram, bool exec) in hwsq_exec() argument
78 if (ram->subdev) { in hwsq_exec()
79 ret = nvkm_hwsq_fini(&ram->hwsq, exec); in hwsq_exec()
80 ram->subdev = NULL; in hwsq_exec()
86 hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) in hwsq_rd32() argument
88 struct nvkm_device *device = ram->subdev->device; in hwsq_rd32()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bus/ |
| D | hwsq.h | 61 hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev) in hwsq_init() argument
65 ret = nvkm_hwsq_init(subdev, &ram->hwsq); in hwsq_init()
69 ram->sequence++; in hwsq_init()
70 ram->subdev = subdev; in hwsq_init()
75 hwsq_exec(struct hwsq *ram, bool exec) in hwsq_exec() argument
78 if (ram->subdev) { in hwsq_exec()
79 ret = nvkm_hwsq_fini(&ram->hwsq, exec); in hwsq_exec()
80 ram->subdev = NULL; in hwsq_exec()
86 hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) in hwsq_rd32() argument
88 struct nvkm_device *device = ram->subdev->device; in hwsq_rd32()
[all …]
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| /kernel/liteos_a/tools/build/ |
| D | liteos_llvm.ld | 42 } > ram
44 .got ALIGN(0x4) : { *(.got.plt) *(.got) } > ram
50 } > ram
55 } > ram
57 ….gcc_except_table ALIGN (0x8) : { . = .; } > ram .gcc_except_table : { KEEP(*(.gcc_except_table*)…
58 .exception_ranges ALIGN (0x8) : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } > ram
60 .ARM.extab ALIGN(0x4) : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ram
63 …LIGN(0x8) : { __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) ;__exidx_end = .;} > ram*/
64 .ARM.exidx ALIGN(0x8) : { __exidx_start = .; __exidx_end = .;} > ram
66 .eh_frame ALIGN (0x8) : { KEEP (*(.eh_frame)) *(.eh_frame.*); } > ram
[all …]
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| D | liteos.ld | 41 } > ram
43 .got ALIGN(0x4) : { *(.got.plt) *(.got) } > ram
45 ….gcc_except_table ALIGN (0x8) : { . = .; } > ram .gcc_except_table : { KEEP(*(.gcc_except_table*)…
46 .exception_ranges ALIGN (0x8) : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } > ram
48 .ARM.extab ALIGN(0x4) : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ram
51 … ALIGN(0x8) : { __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) ;__exidx_end = .;} > ram
57 } > ram
59 .rel.text : { *(.rel.text) *(.rel.text.*) *(.rel.gnu.linkonce.t*) } > ram
60 .rela.text : { *(.rela.text) *(.rela.text.*) *(.rela.gnu.linkonce.t*) } > ram
61 .rel.data : { *(.rel.data) *(.rel.data.*) *(.rel.gnu.linkonce.d*) } > ram
[all …]
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| /kernel/linux/linux-5.10/Documentation/admin-guide/blockdev/ |
| D | ramdisk.rst | 2 Using the RAM disk block device with Linux
10 4) An Example of Creating a Compressed RAM Disk
16 The RAM disk driver is a way to use main system memory as a block device. It
22 The RAM disk dynamically grows as more space is required. It does this by using
23 RAM from the buffer cache. The driver marks the buffers it is using as dirty
26 The RAM disk supports up to 16 RAM disks by default, and can be reconfigured
27 to support an unlimited number of RAM disks (at your own risk). Just change
31 To use RAM disk support with your system, run './MAKEDEV ram' from the /dev
32 directory. RAM disks are all major number 1, and start with minor number 0
35 The new RAM disk also has the ability to load compressed RAM disk images,
[all …]
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