| /kernel/linux/linux-6.6/Documentation/riscv/ |
| D | patch-acceptance.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 ---------
22 RISC-V has a patchwork instance, where the status of patches can be checked:
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| D | boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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| D | hwprobe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
24 be only be valid if all CPUs in the given set have the same value. Otherwise -1
25 will be returned. For boolean-like keys, the value returned will be a logical
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| D | vm-layout.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
17 ------------------------
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
28 the RISC-V Linux Kernel resides.
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| D | boot-image-header.rst | 2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
10 The following 64-byte header is present in decompressed Linux kernel image::
25 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
31 - This header is also reused to support EFI stub for RISC-V. EFI specification
37 - version field indicate header version number
47 - The "magic" field is deprecated as of version 0.2. In a future
52 - In current header, the flags field has only one field.
58 - Image size is mandatory for boot loader to load kernel image. Booting will
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| D | acpi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ACPI on RISC-V
8 Conversion, 12/2022 of the RISC-V specifications, as defined by tag
9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
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| /kernel/linux/linux-5.10/Documentation/riscv/ |
| D | patch-acceptance.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 -------------------------
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
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| D | boot-image-header.rst | 2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
13 The following 64-byte header is present in decompressed Linux kernel image::
28 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
34 - This header can also be reused to support EFI stub for RISC-V in future. EFI
40 - version field indicate header version number
50 - The "magic" field is deprecated as of version 0.2. In a future
55 - In current header, the flags field has only one field.
61 - Image size is mandatory for boot loader to load kernel image. Booting will
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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| /kernel/linux/linux-5.10/Documentation/translations/it_IT/riscv/ |
| D | patch-acceptance.rst | 1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
[all …]
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| /kernel/linux/linux-6.6/Documentation/translations/it_IT/riscv/ |
| D | patch-acceptance.rst | 1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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| D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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| /kernel/linux/linux-6.6/drivers/cpuidle/ |
| D | Kconfig.riscv | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # RISC-V CPU Idle drivers
7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
14 driver for RISC-V systems. This drivers also supports hierarchical
|
| /kernel/linux/linux-6.6/Documentation/translations/zh_CN/riscv/ |
| D | vm-layout.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/riscv/vm-layout.rst
12 RISC-V Linux上的虚拟内存布局
18 这份文件描述了RISC-V Linux内核使用的虚拟内存布局。
20 32位 RISC-V Linux 内核
23 RISC-V Linux Kernel SV32
24 ------------------------
28 64位 RISC-V Linux 内核
31 RISC-V特权架构文档指出，64位地址 "必须使第63-48位值都等于第47位，否则将发生缺页异常。"：这将虚
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /kernel/linux/linux-6.6/arch/riscv/ |
| D | Kconfig.socs | 12 bool "Renesas RISC-V SoCs"
14 This enables support for the RISC-V based Renesas SoCs.
46 bool "T-HEAD RISC-V SoCs"
50 This enables support for the RISC-V based T-HEAD SoCs.
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| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | perf_callchain.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */
19 (unsigned long __user *)(fp - sizeof(struct stackframe)); in user_backtrace()
49 * $ perf record -e cpu-clock --call-graph fp ./program
50 * $ perf report --call-graph
52 * On RISC-V platform, the program being sampled and the C library
53 * need to be compiled with -fno-omit-frame-pointer, otherwise
62 /* RISC-V does not support perf in guest mode. */ in perf_callchain_user()
63 if (guest_cbs && guest_cbs->is_in_guest()) in perf_callchain_user()
66 fp = regs->s0; in perf_callchain_user()
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| /kernel/linux/linux-6.6/drivers/perf/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-riscv-intc.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
29 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
36 * On RISC-V systems local interrupts are masked or unmasked by writing
44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
56 * are defined as (256 + n) and controlled by n-th bit in andes_intc_irq_mask()
59 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_mask()
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| /kernel/linux/linux-6.6/drivers/media/pci/cx88/ |
| D | cx88-alsa.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cx88-reg.h"
22 #include <linux/dma-mapping.h>
37 chip->core->name, ##arg); \
41 * Data type declarations - Can be moded to a header file later
46 struct cx88_riscmem risc; member
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
115 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
116 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
119 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
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| /kernel/linux/linux-5.10/drivers/media/pci/cx88/ |
| D | cx88-alsa.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cx88-reg.h"
22 #include <linux/dma-mapping.h>
37 chip->core->name, ##arg); \
41 * Data type declarations - Can be moded to a header file later
46 struct cx88_riscmem risc; member
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
116 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
117 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
120 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
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