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/kernel/linux/linux-6.6/Documentation/networking/devlink/
Ddevlink-dpipe.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
36 In many situations trying to analyze systems failure solely based on the
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
56 using Ternary Content Addressable Memory (TCAM). The TCAM memory can be
57 divided into TCAM regions. Complex TC filters can have multiple rules with
59 TCAM regions have a predefined lookup key. Offloading the TC filter rules
[all …]
/kernel/linux/linux-5.10/Documentation/networking/devlink/
Ddevlink-dpipe.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
36 In many situations trying to analyze systems failure solely based on the
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
56 using Ternary Content Addressable Memory (TCAM). The TCAM memory can be
57 divided into TCAM regions. Complex TC filters can have multiple rules with
59 TCAM regions have a predefined lookup key. Offloading the TC filter rules
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
[all …]
/kernel/linux/linux-5.10/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
17 bool "Allwinner sunxi 64-bit SoC Family"
23 This enables support for Allwinner sunxi based SoCs like the A64.
52 This enables support for Broadcom iProc based SoCs
69 bool "Broadcom Set-Top-Box SoCs"
79 bool "ARMv8 based Samsung Exynos SoC family"
90 This enables support for ARMv8 based Samsung Exynos SoC family.
93 bool "ARMv8 based Microchip Sparx5 SoC family"
97 This enables support for the Microchip Sparx5 ARMv8-based
98 SoC family of TSN-capable gigabit switches.
[all …]
/kernel/linux/linux-6.6/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
12 bool "Allwinner sunxi 64-bit SoC Family"
20 This enables support for Allwinner sunxi based SoCs like the A64.
33 This enables support for Apple's in-house ARM SoC family, starting
61 This enables support for Broadcom iProc based SoCs
67 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
70 This enables support for Broadcom BCA ARM-based broadband chipsets,
74 bool "Broadcom Set-Top-Box SoCs"
108 This enables support for ARMv8 based Samsung Exynos SoC family.
115 This enables support for the Microchip Sparx5 ARMv8-based
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/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/
Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
77 * ice_sect_id - returns section ID
90 * ice_hw_ptype_ena - check if the PTYPE is enabled or not
97 test_bit(ptype, hw->hw_ptype); in ice_hw_ptype_ena()
112 * ice_gen_key_word - generate 16-bits of a key/mask word
120 * This function generates 16-bits from a 8-bit value, an 8-bit don't care mask
121 * and an 8-bit never match mask. The 16-bits of output are divided into 8 bits
133 * ------------------------------
145 return -EIO; in ice_gen_key_word()
150 /* encode the 8 bits into 8-bit key and 8-bit key invert */ in ice_gen_key_word()
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Dice_ddp.c1 // SPDX-License-Identifier: GPL-2.0
9 * boost tcam entries. The metadata labels names that match the following
26 * ice_verify_pkg - verify package
41 if (pkg->pkg_format_ver.major != ICE_PKG_FMT_VER_MAJ || in ice_verify_pkg()
42 pkg->pkg_format_ver.minor != ICE_PKG_FMT_VER_MNR || in ice_verify_pkg()
43 pkg->pkg_format_ver.update != ICE_PKG_FMT_VER_UPD || in ice_verify_pkg()
44 pkg->pkg_format_ver.draft != ICE_PKG_FMT_VER_DFT) in ice_verify_pkg()
48 seg_count = le32_to_cpu(pkg->seg_count); in ice_verify_pkg()
58 u32 off = le32_to_cpu(pkg->seg_offset[i]); in ice_verify_pkg()
68 if (len < off + le32_to_cpu(seg->seg_size)) in ice_verify_pkg()
[all …]
Dice_vlan_mode.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2021, Intel Corporation. */
7 * ice_pkg_get_supported_vlan_mode - determine if DDP supports Double VLAN mode
26 return -ENOMEM; in ice_pkg_get_supported_vlan_mode()
29 sect->count = cpu_to_le16(1); in ice_pkg_get_supported_vlan_mode()
30 sect->offset = cpu_to_le16(ICE_META_VLAN_MODE_ENTRY); in ice_pkg_get_supported_vlan_mode()
42 arr[i] = le32_to_cpu(sect->entry.bm[i]); in ice_pkg_get_supported_vlan_mode()
56 * ice_aq_get_vlan_mode - get the VLAN mode of the device
58 * @get_params: structure FW fills in based on the current VLAN mode config
69 return -EINVAL; in ice_aq_get_vlan_mode()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
85 * ice_sect_id - returns section ID
109 hdr = (struct ice_buf_hdr *)buf->buf; in ice_pkg_val_buf()
111 section_count = le16_to_cpu(hdr->section_count); in ice_pkg_val_buf()
115 data_end = le16_to_cpu(hdr->data_end); in ice_pkg_val_buf()
133 (ice_seg->device_table + in ice_find_buf_table()
134 le32_to_cpu(ice_seg->device_table_count)); in ice_find_buf_table()
137 (nvms->vers + le32_to_cpu(nvms->table_count)); in ice_find_buf_table()
146 * call is made with the ice_seg parameter non-NULL; on subsequent calls,
156 state->buf_table = ice_find_buf_table(ice_seg); in ice_pkg_enum_buf()
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/kernel/linux/linux-6.6/drivers/net/ethernet/mscc/
Docelot_vcap.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
40 u32 tg_sw; /* Current type-group */
45 u32 tg_value; /* Current type-group value */
46 u32 tg_mask; /* Current type-group mask */
52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); in vcap_read_update_ctrl()
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL); in vcap_cmd()
81 /* Convert from 0-based row to VCAP entry row and run command */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/mscc/
Docelot_vcap.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
40 u32 tg_sw; /* Current type-group */
45 u32 tg_value; /* Current type-group value */
46 u32 tg_mask; /* Current type-group mask */
52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); in vcap_read_update_ctrl()
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL); in vcap_cmd()
81 /* Convert from 0-based row to VCAP entry row and run command */
[all …]
/kernel/linux/linux-6.6/net/dsa/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 tristate "No-op tag driver"
28 tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
31 the Atheros AR9331 SoC with built-in switch.
38 tristate "Tag driver for Broadcom switches using in-frame headers"
45 tristate "Tag driver for Broadcom legacy switches using in-frame headers"
108 hardware-defined injection/extraction frame header. Flow control
116 custom VLAN-based header. Frames that require timestamping, such as
117 PTP, are not delivered over Ethernet but over register-based MMIO.
119 this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
[all …]
Dtag_ocelot_8021q.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2020-2021 NXP
4 * An implementation of the software-defined tag_8021q.c tagger format, which
6 * this by using the TCAM engines for:
7 * - pushing the RX VLAN as a second, outer tag, on egress towards the CPU port
8 * - redirecting towards the correct front port based on TX VLAN and popping
17 #define OCELOT_8021Q_NAME "ocelot-8021q"
27 struct ocelot_8021q_tagger_private *priv = dp->ds->tagger_data; in ocelot_defer_xmit()
28 struct ocelot_8021q_tagger_data *data = &priv->data; in ocelot_defer_xmit()
33 xmit_work_fn = data->xmit_work_fn; in ocelot_defer_xmit()
[all …]
Dtag_8021q.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Binary structure of the fake 12-bit VID field (when the TPID is
19 * +-----------+-----+-----------------+-----------+-----------------------+
21 * +-----------+-----+-----------------+-----------+-----------------------+
23 * RSV - VID[11:10]:
26 * SWITCH_ID - VID[8:6]:
29 * VBID - { VID[9], VID[5:4] }:
34 * PORT - VID[3:0]:
94 return DSA_8021Q_RSV | DSA_8021Q_SWITCH_ID(dp->ds->index) | in dsa_tag_8021q_standalone_vid()
95 DSA_8021Q_PORT(dp->index); in dsa_tag_8021q_standalone_vid()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
72 /* SMID - Switch Multicast ID
73 * --------------------------
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/kernel/linux/linux-6.6/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
72 /* SSPR - Switch System Port Record Register
73 * -----------------------------------------
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/freescale/dpaa2/
Ddpni.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2016 Freescale Semiconductor Inc.
32 #define DPNI_ALL_TCS (u8)(-1)
36 #define DPNI_ALL_TC_FLOWS (u16)(-1)
40 #define DPNI_NEW_FLOW_ID (u16)(-1)
56 * Allocate policers for this DPNI. They can be used to rate-limit traffic per
69 * Enables TCAM for Flow Steering and QoS look-ups. If not specified, all
70 * look-ups are exact match. Note that TCAM is not available on LS1088 and its
93 * struct dpni_pools_cfg - Structure representing buffer pools configuration
185 * struct dpni_attr - Structure representing DPNI attributes
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/freescale/dpaa2/
Ddpni.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2016 Freescale Semiconductor Inc.
20 * DPNI_MAX_TC - Maximum number of traffic classes
24 * DPNI_MAX_DPBP - Maximum number of buffer pools per DPNI
29 * DPNI_ALL_TCS - All traffic classes considered; see dpni_set_queue()
31 #define DPNI_ALL_TCS (u8)(-1)
33 * DPNI_ALL_TC_FLOWS - All flows within traffic class considered; see
36 #define DPNI_ALL_TC_FLOWS (u16)(-1)
38 * DPNI_NEW_FLOW_ID - Generate new flow ID; see dpni_set_queue()
40 #define DPNI_NEW_FLOW_ID (u16)(-1)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2.h1 /* SPDX-License-Identifier: GPL-2.0 */
346 /* Packet Processor per-port counters */
407 /* Per-port registers */
472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
473 * relative to port->base.
509 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */
513 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
583 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
692 /* Maximum number of T-CONTs of PON port */
729 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2.h1 /* SPDX-License-Identifier: GPL-2.0 */
355 /* Packet Processor per-port counters */
420 /* Per-port registers */
485 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
486 * relative to port->base.
522 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
526 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
596 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
714 /* Maximum number of T-CONTs of PON port */
754 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
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/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_filter.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
65 return -ENOMEM; in set_tcb_field()
69 req->reply_ctrl = htons(REPLY_CHAN_V(0) | in set_tcb_field()
70 QUEUENO_V(adap->sge.fw_evtq.abs_id) | in set_tcb_field()
72 req->word_cookie = htons(TCB_WORD_V(word) | TCB_COOKIE_V(ftid)); in set_tcb_field()
73 req->mask = cpu_to_be64(mask); in set_tcb_field()
74 req->val = cpu_to_be64(val); in set_tcb_field()
75 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); in set_tcb_field()
[all …]

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