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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/marvell/
Dcp110-system-controller.txt1 Marvell Armada CP110 System Controller
4 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
14 SYSTEM CONTROLLER 0
18 -------
20 The Device Tree node representing this System Controller 0 provides a
23 - a set of core clocks
24 - a set of gatable clocks
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/marvell/
Dcp110-system-controller.txt1 Marvell Armada CP110 System Controller
4 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
14 SYSTEM CONTROLLER 0
18 -------
20 The Device Tree node representing this System Controller 0 provides a
23 - a set of core clocks
24 - a set of gateable clocks
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/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
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Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
11 * called NFCv2 and is available on Armada SoCs.
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
26 * controller when Hamming is chosen:
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
36 * 30B per ECC chunk. Here is the page layout used by the controller
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
45 Enable the driver for NAND flash on Intel Moorestown, using the
46 Denali NAND controller core.
[all …]
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
11 * called NFCv2 and is available on Armada SoCs.
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
26 * controller when Hamming is chosen:
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
36 * 30B per ECC chunk. Here is the page layout used by the controller
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt3 The Device Bus controller available in some Marvell's SoC allows to control
4 different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
17 the controller's register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt3 The Device Bus controller available in some Marvell's SoC allows to control
4 different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
17 the controller's register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
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/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 model = "Marvell Armada 88AP510 SoC";
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 model = "Marvell Armada 88AP510 SoC";
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
[all …]
/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
54 K: *Content regex* (perl extended) pattern match in a patch or file.
56 K: of_get_profile
58 K: \b(printk|pr_(info|err))\b
61 One regex pattern per line. Multiple K: lines acceptable.
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
78 8. Happy hacking.
81 ---------------------------------------------------
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