| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | frontend.json | 15 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
53 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
65 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
107 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
113 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
119 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
125 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | frontend.json | 6 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
29 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
40 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
51 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
89 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
95 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
100 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
106 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/rocketlake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/meteorlake/ |
| D | frontend.json | 15 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
73 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
85 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
136 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
142 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
148 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
154 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 121 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
128 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
132 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
139 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
154 …ed to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
165 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
177 …vered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back…
185 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
190 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
197 "BriefDescription": "DSB-to-MITE switch true penalty cycles."
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | pipeline.json | 214 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.…
222 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r…
287 "BriefDescription": "Self-Modifying Code detected",
290 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
295 "BriefDescription": "Uops issued to the back end per cycle",
298 …end and allocated into the back end of the machine. This event counts uops that retire as well as…
302 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
305 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
330 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/skylake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | pipeline.json | 205 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature",
223 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.…
231 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r…
299 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store…
304 "BriefDescription": "Self-Modifying Code detected",
307 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
312 "BriefDescription": "Uops issued to the back end per cycle",
315 …end and allocated into the back end of the machine. This event counts uops that retire as well as…
319 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
322 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylake/ |
| D | frontend.json | 158 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
167 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
180 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
190 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
201 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
212 "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
218 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
223 "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
229 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
245 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | frontend.json | 27 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
40 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
46 "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
68 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
73 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
78 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
83 …Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) mi…
91 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
103 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
108 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | frontend.json | 9 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
37 … an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was no…
50 … an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was no…
63 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
71 …e delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycle…
111 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
117 "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
133 …Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) mi…
141 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
184 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | pipeline.json | 83 …end and allocated into the back end of the machine. This event counts uops that retire as well as…
89 "BriefDescription": "Uops issued to the back end per cycle"
113 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
119 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
146 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
188 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
194 "BriefDescription": "Self-Modifying Code detected"
|
| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
56 * A single branch back-end of the CCS PLL tree.
71 * struct ccs_pll - Full CCS PLL configuration
78 * @csi2: CSI-2 related parameters
[all …]
|
| /kernel/linux/linux-6.6/fs/erofs/ |
| D | namei.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2018 HUAWEI, Inc.
12 const unsigned char *end; member
15 /* based on the end of qn is accurate and it must have the trailing '\0' */
23 * on-disk error, let's only BUG_ON in the debugging mode. in erofs_dirnamecmp()
27 DBG_BUGON(qd->name > qd->end); in erofs_dirnamecmp()
30 /* However it is absolutely safe if < qd->end */ in erofs_dirnamecmp()
31 while (qd->name + i < qd->end && qd->name[i] != '\0') { in erofs_dirnamecmp()
32 if (qn->name[i] != qd->name[i]) { in erofs_dirnamecmp()
34 return qn->name[i] > qd->name[i] ? 1 : -1; in erofs_dirnamecmp()
[all …]
|
| /kernel/linux/linux-5.10/fs/erofs/ |
| D | namei.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2018 HUAWEI, Inc.
13 const unsigned char *end; member
16 /* based on the end of qn is accurate and it must have the trailing '\0' */
24 * on-disk error, let's only BUG_ON in the debugging mode. in erofs_dirnamecmp()
28 DBG_BUGON(qd->name > qd->end); in erofs_dirnamecmp()
31 /* However it is absolutely safe if < qd->end */ in erofs_dirnamecmp()
32 while (qd->name + i < qd->end && qd->name[i] != '\0') { in erofs_dirnamecmp()
33 if (qn->name[i] != qd->name[i]) { in erofs_dirnamecmp()
35 return qn->name[i] > qd->name[i] ? 1 : -1; in erofs_dirnamecmp()
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_asrc_dma.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
11 #include <linux/platform_data/dma-imx.h>
37 chan->private = param; in filter()
45 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_asrc_dma_complete()
46 struct fsl_asrc_pair *pair = runtime->private_data; in fsl_asrc_dma_complete()
48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete()
49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete()
50 pair->pos = 0; in fsl_asrc_dma_complete()
58 u8 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? OUT : IN; in fsl_asrc_dma_prepare_and_submit()
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| D | fsl_asrc_dma.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
11 #include <linux/dma/imx-dma.h>
37 chan->private = param; in filter()
45 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_asrc_dma_complete()
46 struct fsl_asrc_pair *pair = runtime->private_data; in fsl_asrc_dma_complete()
48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete()
49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete()
50 pair->pos = 0; in fsl_asrc_dma_complete()
58 u8 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? OUT : IN; in fsl_asrc_dma_prepare_and_submit()
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/graniterapids/ |
| D | frontend.json | 3 … were no operation was delivered to the back-end pipeline due to instruction fetch limitations whe…
6 …back-end pipeline due to instruction fetch limitations when the back-end could have accepted more …
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | pipeline.json | 98 …end and allocated into the back end of the machine. This event counts uops that retire as well as…
106 "BriefDescription": "Uops issued to the back end per cycle"
134 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
142 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
165 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature"
183 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
231 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
239 "BriefDescription": "Self-Modifying Code detected"
267 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store…
|
| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | cache-sh2a.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2a.c
47 * Write back the dirty D-caches, but not invalidate them.
53 unsigned long begin, end; in sh2a__flush_wback_region() local
57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_wback_region()
59 & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
66 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { in sh2a__flush_wback_region()
68 end = begin + (nr_ways * current_cpu_data.dcache.way_size); in sh2a__flush_wback_region()
70 for (v = begin; v < end; v += L1_CACHE_BYTES) { in sh2a__flush_wback_region()
[all …]
|