Searched +full:bias +full:- +full:pull +full:- +full:pin +full:- +full:default (Results 1 – 25 of 330) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-sx150x.txt | 3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
5 pin controller, GPIO, and interrupt bindings.
8 - compatible: should be one of :
19 - reg: The I2C slave address for this device.
21 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
25 - gpio-controller: Marks the device as a GPIO controller.
28 - interrupts: Interrupt specifier for the controllers interrupt.
30 - interrupt-controller: Marks the device as a interrupt controller.
32 - semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
[all …]
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| D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic pin configuration node schema
10 - Linus Walleij <linus.walleij@linaro.org>
13 Many data items that are represented in a pin configuration node are common
14 and generic. Pin control bindings should use the properties defined below
21 bias-disable:
23 description: disable any pin bias
[all …]
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| D | ti,da850-pupd.txt | 1 * Pin configuration for TI DA850/OMAP-L138/AM18x
3 These SoCs have a separate controller for setting bias (internal pullup/down).
4 Bias can only be selected for groups rather than individual pins.
8 - compatible: Must be "ti,da850-pupd"
9 - reg: Base address and length of the memory resource used by the pullup/down
12 The controller node also acts as a container for pin group configuration nodes.
15 Pin Group Node Properties:
17 - groups: An array of strings, each string containing the name of a pin group.
20 The pin configuration parameters use the generic pinconf bindings defined in
21 pinctrl-bindings.txt in this directory. The supported parameters are
[all …]
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| D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
[all …]
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| D | pinctrl-palmas.txt | 4 the configuration for Pull UP/DOWN, open drain etc.
7 - compatible: It must be one of following:
8 - "ti,palmas-pinctrl" for Palma series of the pincontrol.
9 - "ti,tps65913-pinctrl" for Palma series device TPS65913.
10 - "ti,tps80036-pinctrl" for Palma series device TPS80036.
12 Please refer to pinctrl-bindings.txt in this directory for details of the
14 phrase "pin configuration node".
16 Palmas's pin configuration nodes act as a container for an arbitrary number of
19 those pin(s), and various pin configuration parameters, such as pull-up,
26 other words, a subnode that lists a mux function but no pin configuration
[all …]
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| D | qcom,ipq8064-pinctrl.txt | 4 - compatible: "qcom,ipq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| D | qcom,msm8974-pinctrl.txt | 4 - compatible: "qcom,msm8974-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| D | qcom,msm8660-pinctrl.txt | 4 - compatible: "qcom,msm8660-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Configuration Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 Many data items that are represented in a pin configuration node are common
14 and generic. Pin control bindings should use the properties defined below
21 bias-disable:
23 description: disable any pin bias
[all …]
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| D | ti,da850-pupd.txt | 1 * Pin configuration for TI DA850/OMAP-L138/AM18x
3 These SoCs have a separate controller for setting bias (internal pullup/down).
4 Bias can only be selected for groups rather than individual pins.
8 - compatible: Must be "ti,da850-pupd"
9 - reg: Base address and length of the memory resource used by the pullup/down
12 The controller node also acts as a container for pin group configuration nodes.
15 Pin Group Node Properties:
17 - groups: An array of strings, each string containing the name of a pin group.
20 The pin configuration parameters use the generic pinconf bindings defined in
21 pinctrl-bindings.txt in this directory. The supported parameters are
[all …]
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| D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
[all …]
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| D | socionext,uniphier-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: UniPhier SoCs pin controller
11 - Masahiro Yamada <yamada.masahiro@socionext.com>
16 - socionext,uniphier-ld4-pinctrl
17 - socionext,uniphier-pro4-pinctrl
18 - socionext,uniphier-sld8-pinctrl
19 - socionext,uniphier-pro5-pinctrl
[all …]
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| D | pinctrl-palmas.txt | 4 the configuration for Pull UP/DOWN, open drain etc.
7 - compatible: It must be one of following:
8 - "ti,palmas-pinctrl" for Palma series of the pincontrol.
9 - "ti,tps65913-pinctrl" for Palma series device TPS65913.
10 - "ti,tps80036-pinctrl" for Palma series device TPS80036.
12 Please refer to pinctrl-bindings.txt in this directory for details of the
14 phrase "pin configuration node".
16 Palmas's pin configuration nodes act as a container for an arbitrary number of
19 those pin(s), and various pin configuration parameters, such as pull-up,
26 other words, a subnode that lists a mux function but no pin configuration
[all …]
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| D | rockchip,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Please refer to pinctrl-bindings.txt in this directory for details of the
20 phrase "pin configuration node".
22 The Rockchip pin configuration node is a node of a group of pins which can be
25 (also named pin mode) this pin can work on and the 'config' configures
26 various pad settings such as pull-up, etc.
28 The pins are grouped into up to 9 individual pin banks which need to be
[all …]
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| D | atmel,at91-pio4-pinctrl.txt | 3 The Atmel PIO4 controller is used to select the function of a pin and to
7 - compatible:
8 "atmel,sama5d2-pinctrl"
9 "microchip,sama7g5-pinctrl"
10 - reg: base address and length of the PIO controller.
11 - interrupts: interrupt outputs from the controller, one for each bank.
12 - interrupt-controller: mark the device node as an interrupt controller.
13 - #interrupt-cells: should be two.
14 - gpio-controller: mark the device node as a gpio controller.
15 - #gpio-cells: should be two.
[all …]
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| D | qcom,ipq8064-pinctrl.txt | 4 - compatible: "qcom,ipq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| D | semtech,sx1501q.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - semtech,sx1501q
17 - semtech,sx1502q
18 - semtech,sx1503q
19 - semtech,sx1504q
20 - semtech,sx1505q
21 - semtech,sx1506q
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | lpc4357-myd-lpc4357.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
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| D | qcom-apq8064-sony-xperia-yuga.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 compatible = "sony,xperia-yuga", "qcom,apq8064";
17 stdout-path = "serial0:115200n8";
20 gpio-keys {
21 compatible = "gpio-keys";
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/lpc/ |
| D | lpc4357-myd-lpc4357.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | sc7280-idp.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
9 #include <dt-bindings/input/linux-event-codes.h>
15 #include "sc7280-chrome-common.dtsi"
16 #include "sc7280-herobrine-lte-sku.dtsi"
25 max98360a: audio-codec-0 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&_en>;
29 sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
30 #sound-dai-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt7622-rfb1.dts | 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
[all …]
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| D | mt7622-bananapi-bpi-r64.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/ |
| D | qcom-apq8064-sony-xperia-lagan-yuga.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 compatible = "sony,xperia-yuga", "qcom,apq8064";
11 chassis-type = "handset";
18 stdout-path = "serial0:115200n8";
21 gpio-keys {
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt7622-rfb1.dts | 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
[all …]
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