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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
[all …]
Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
[all …]
Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
/kernel/linux/linux-5.10/drivers/dma/dw-edma/
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
18 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
45 struct dw_edma_burst *burst; in dw_edma_alloc_burst() local
47 burst = kzalloc(sizeof(*burst), GFP_NOWAIT); in dw_edma_alloc_burst()
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
37 u32 cs_wr_off; /* Write deassertion time */
42 u32 adv_wr_off; /* Write deassertion time */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
61 u32 wr_cycle; /* Total write cycle time */
97 u32 t_cez_w; /* write CS deassertion to high Z */
100 u32 t_wpl; /* write assertion time */
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
37 u32 cs_wr_off; /* Write deassertion time */
42 u32 adv_wr_off; /* Write deassertion time */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
61 u32 wr_cycle; /* Total write cycle time */
97 u32 t_cez_w; /* write CS deassertion to high Z */
100 u32 t_wpl; /* write assertion time */
[all …]
/kernel/linux/linux-5.10/drivers/dma/qcom/
Dhidma_mgmt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
20 #include <linux/dma-mapping.h>
48 "maximum write burst (default: ACPI/DT value)");
53 "maximum read burst (default: ACPI/DT value)");
58 "maximum number of write transactions (default: ACPI/DT value)");
70 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
71 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
72 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
73 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
[all …]
/kernel/linux/linux-6.6/drivers/dma/qcom/
Dhidma_mgmt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
22 #include <linux/dma-mapping.h>
50 "maximum write burst (default: ACPI/DT value)");
55 "maximum read burst (default: ACPI/DT value)");
60 "maximum number of write transactions (default: ACPI/DT value)");
72 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
73 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
74 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
75 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
[all …]
/kernel/linux/linux-6.6/include/linux/iio/imu/
Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 * struct adis_timeouts - ADIS chip variant timeouts
27 * @reset_ms - Wait time after rst pin goes inactive
28 * @sw_reset_ms - Wait time after sw reset command
29 * @self_test_ms - Wait time after self test command
38 * struct adis_data - ADIS chip variant specific data
40 * @write_delay: SPI delay for write operations in us
47 * @self_test_mask: Bitmask of supported self-test operations
49 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
[all …]
/kernel/linux/linux-6.6/drivers/misc/
Ddw-xdata-pcie.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-epf.h>
20 #define DW_XDATA_DRIVER_NAME "dw-xdata-pcie"
75 return dw->rg_region.vaddr; in __dw_regs()
80 u32 burst; in dw_xdata_stop() local
82 mutex_lock(&dw->mutex); in dw_xdata_stop()
84 burst = readl(&(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
86 if (burst & BURST_REPEAT) { in dw_xdata_stop()
87 burst &= ~(u32)BURST_REPEAT; in dw_xdata_stop()
88 writel(burst, &(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
[all …]
/kernel/linux/linux-5.10/include/linux/iio/imu/
Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
25 * struct adis_timeouts - ADIS chip variant timeouts
26 * @reset_ms - Wait time after rst pin goes inactive
27 * @sw_reset_ms - Wait time after sw reset command
28 * @self_test_ms - Wait time after self test command
37 * struct adis_data - ADIS chip variant specific data
39 * @write_delay: SPI delay for write operations in us
46 * @self_test_mask: Bitmask of supported self-test operations
48 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "ti,omap2-onenand";
[all …]
/kernel/linux/linux-6.6/drivers/dma/dw-edma/
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
[all …]
/kernel/linux/linux-6.6/drivers/char/tpm/
Dtpm_tis_i2c_cr50.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
45 * struct tpm_i2c_cr50_priv_data - Driver private data.
60 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
74 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
76 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/tw5864/
Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
[all …]
/kernel/linux/linux-6.6/drivers/media/pci/tw5864/
Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
[all …]
/kernel/linux/linux-6.6/include/linux/mtd/
Dhyperbus.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
51 * send cmd to flash or write single 16 bit word at a time.
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
[all …]
/kernel/linux/linux-5.10/include/linux/mtd/
Dhyperbus.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
51 * send cmd to flash or write single 16 bit word at a time.
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]

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