| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | cacheinfo.c | 3 * Processor cache information made available to userspace via sysfs;
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
53 /* Allow for both [di]-cache-line-size and
54 * [di]-cache-block-size properties. According to the PowerPC
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| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | cacheinfo.c | 3 * Processor cache information made available to userspace via sysfs;
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
52 /* Allow for both [di]-cache-line-size and
53 * [di]-cache-block-size properties. According to the PowerPC
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| /kernel/linux/linux-6.6/fs/fscache/ |
| D | cache.c | 2 /* FS-Cache cache handling
8 #define FSCACHE_DEBUG_LEVEL CACHE
22 * Allocate a cache cookie.
26 struct fscache_cache *cache; in fscache_alloc_cache() local
28 cache = kzalloc(sizeof(*cache), GFP_KERNEL); in fscache_alloc_cache()
29 if (cache) { in fscache_alloc_cache()
31 cache->name = kstrdup(name, GFP_KERNEL); in fscache_alloc_cache()
32 if (!cache->name) { in fscache_alloc_cache()
33 kfree(cache); in fscache_alloc_cache()
37 refcount_set(&cache->ref, 1); in fscache_alloc_cache()
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| /kernel/linux/linux-6.6/drivers/md/ |
| D | dm-cache-target.c | 11 #include "dm-cache-metadata.h"
13 #include "dm-cache-background-tracker.h"
25 #define DM_MSG_PREFIX "cache"
28 "A percentage of time allocated for copying to and/or from cache");
36 * cblock: index of a cache block
37 * promotion: movement of a block from origin to cache
38 * demotion: movement of a block from cache to origin
39 * migration: movement of a block between the origin and cache device,
242 * The block size of the device holding cache data must be
257 * dirty. If you lose the cache device you will lose data.
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| /kernel/linux/linux-5.10/drivers/md/ |
| D | dm-cache-target.c | 10 #include "dm-cache-metadata.h"
22 #define DM_MSG_PREFIX "cache"
25 "A percentage of time allocated for copying to and/or from cache");
33 * cblock: index of a cache block
34 * promotion: movement of a block from origin to cache
35 * demotion: movement of a block from cache to origin
36 * migration: movement of a block between the origin and cache device,
310 * The block size of the device holding cache data must be
325 * dirty. If you lose the cache device you will lose data.
331 * Data is written to both cache and origin. Blocks are never
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| /kernel/linux/linux-5.10/fs/cachefiles/ |
| D | bind.c | 2 /* Bind and unbind a cache from the filesystem backing it
25 * bind a directory as a cache
27 int cachefiles_daemon_bind(struct cachefiles_cache *cache, char *args) in cachefiles_daemon_bind() argument
30 cache->frun_percent, in cachefiles_daemon_bind()
31 cache->fcull_percent, in cachefiles_daemon_bind()
32 cache->fstop_percent, in cachefiles_daemon_bind()
33 cache->brun_percent, in cachefiles_daemon_bind()
34 cache->bcull_percent, in cachefiles_daemon_bind()
35 cache->bstop_percent, in cachefiles_daemon_bind()
39 ASSERT(cache->fstop_percent >= 0 && in cachefiles_daemon_bind()
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| /kernel/linux/linux-6.6/fs/cachefiles/ |
| D | cache.c | 2 /* Manage high-level VFS aspects of a cache.
15 * Bring a cache online.
17 int cachefiles_add_cache(struct cachefiles_cache *cache) in cachefiles_add_cache() argument
28 cache_cookie = fscache_acquire_cache(cache->tag); in cachefiles_add_cache()
33 ret = cachefiles_get_security_ID(cache); in cachefiles_add_cache()
37 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_add_cache()
39 /* look up the directory at the root of the cache */ in cachefiles_add_cache()
40 ret = kern_path(cache->rootdirname, LOOKUP_DIRECTORY, &path); in cachefiles_add_cache()
44 cache->mnt = path.mnt; in cachefiles_add_cache()
49 pr_warn("File cache on idmapped mounts not supported"); in cachefiles_add_cache()
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| D | daemon.c | 62 int (*handler)(struct cachefiles_cache *cache, char *args);
88 * Prepare a cache for caching.
92 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
104 /* allocate a cache record */ in cachefiles_daemon_open()
105 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
106 if (!cache) { in cachefiles_daemon_open()
111 mutex_init(&cache->daemon_mutex); in cachefiles_daemon_open()
112 init_waitqueue_head(&cache->daemon_pollwq); in cachefiles_daemon_open()
113 INIT_LIST_HEAD(&cache->volumes); in cachefiles_daemon_open()
114 INIT_LIST_HEAD(&cache->object_list); in cachefiles_daemon_open()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z16/ |
| D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 …on Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replace…
21 … request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for th…
42 …ion Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replace…
49 …ade by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the L…
91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
97 "BriefDescription": "Directory Write Level 1 Data Cache from Cache",
98 …tory write to the Level-1 Data cache directory where the returned cache line was sourced from the …
104 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
105 …tory write to the Level-1 Data cache directory where the returned cache line was sourced from the …
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&cluster0_l2>;
42 d-cache-size = <0x8000>;
43 d-cache-line-size = <64>;
44 d-cache-sets = <256>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-cpus.dtsi | 49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <256>;
55 l2-cache = <&L2_0>;
65 i-cache-size = <0xC000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
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| /kernel/linux/linux-5.10/fs/fscache/ |
| D | cache.c | 2 /* FS-Cache cache handling
8 #define FSCACHE_DEBUG_LEVEL CACHE
21 * look up a cache tag
67 * release a reference to a cache tag
86 * select a cache in which to store an object
87 * - the cache addremove semaphore must be at least read-locked by the caller
95 struct fscache_cache *cache; in fscache_select_cache_for_object() local
100 _leave(" = NULL [no cache]"); in fscache_select_cache_for_object()
104 /* we check the parent to determine the cache to use */ in fscache_select_cache_for_object()
108 * cache */ in fscache_select_cache_for_object()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&cluster0_l2>;
42 d-cache-size = <0x8000>;
43 d-cache-line-size = <64>;
44 d-cache-sets = <256>;
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| /kernel/linux/linux-5.10/fs/ |
| D | mbcache.c | 16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
50 static inline struct hlist_bl_head *mb_cache_entry_head(struct mb_cache *cache, in mb_cache_entry_head() argument
53 return &cache->c_hash[hash_32(key, cache->c_bucket_bits)]; in mb_cache_entry_head()
58 * in cache
63 * mb_cache_entry_create - create entry in cache
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
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| D | socionext,uniphier-system-cache.yaml | 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
19 const: socionext,uniphier-system-cache
29 Interrupts can be used to notify the completion of cache operations.
35 cache-unified: true
37 cache-size: true
39 cache-sets: true
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| /kernel/linux/linux-6.6/fs/ |
| D | mbcache.c | 16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
50 static inline struct hlist_bl_head *mb_cache_entry_head(struct mb_cache *cache, in mb_cache_entry_head() argument
53 return &cache->c_hash[hash_32(key, cache->c_bucket_bits)]; in mb_cache_entry_head()
58 * in cache
63 * mb_cache_entry_create - create entry in cache
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| /kernel/linux/linux-5.10/arch/loongarch/boot/dts/loongson/ |
| D | loongson3.dtsi | 15 l2-cache = <&vcache0>;
16 next-level-cache = <&scache0>;
23 l2-cache = <&vcache1>;
24 next-level-cache = <&scache0>;
31 l2-cache = <&vcache2>;
32 next-level-cache = <&scache0>;
39 l2-cache = <&vcache3>;
40 next-level-cache = <&scache0>;
47 l2-cache = <&vcache4>;
48 next-level-cache = <&scache1>;
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | cache.json | 23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59 "BriefDescription": "Demand data cache fills from extension memory.",
65 "BriefDescription": "Demand data cache fills from all types of data sources.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
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| /kernel/linux/linux-6.6/fs/squashfs/ |
| D | cache.c | 8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
49 * Look-up block in cache, and increment usage count. If not in cache, read
53 struct squashfs_cache *cache, u64 block, int length) in squashfs_cache_get() argument
58 spin_lock(&cache->lock); in squashfs_cache_get()
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| /kernel/linux/linux-5.10/fs/squashfs/ |
| D | cache.c | 8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
49 * Look-up block in cache, and increment usage count. If not in cache, read
53 struct squashfs_cache *cache, u64 block, int length) in squashfs_cache_get() argument
58 spin_lock(&cache->lock); in squashfs_cache_get()
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
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| /kernel/linux/linux-5.10/mm/ |
| D | swap_slots.c | 3 * Manage cache of swap slots to be used for and returned from
25 * The swap slots cache is protected by a mutex instead of
42 /* Serialize swap slots cache enable/disable operations */
107 /* if global pool of slot caches too low, deactivate cache */ in check_cache_active()
116 struct swap_slots_cache *cache; in alloc_swap_slot_cache() local
137 cache = &per_cpu(swp_slots, cpu); in alloc_swap_slot_cache()
138 if (cache->slots || cache->slots_ret) { in alloc_swap_slot_cache()
139 /* cache already allocated */ in alloc_swap_slot_cache()
148 if (!cache->lock_initialized) { in alloc_swap_slot_cache()
149 mutex_init(&cache->alloc_lock); in alloc_swap_slot_cache()
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| /kernel/linux/linux-6.6/mm/ |
| D | swap_slots.c | 3 * Manage cache of swap slots to be used for and returned from
25 * The swap slots cache is protected by a mutex instead of
43 /* Serialize swap slots cache enable/disable operations */
106 /* if global pool of slot caches too low, deactivate cache */ in check_cache_active()
115 struct swap_slots_cache *cache; in alloc_swap_slot_cache() local
136 cache = &per_cpu(swp_slots, cpu); in alloc_swap_slot_cache()
137 if (cache->slots || cache->slots_ret) { in alloc_swap_slot_cache()
138 /* cache already allocated */ in alloc_swap_slot_cache()
147 if (!cache->lock_initialized) { in alloc_swap_slot_cache()
148 mutex_init(&cache->alloc_lock); in alloc_swap_slot_cache()
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|