| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
22 struct iproc_asiu_div div; member
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
47 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
32 struct iproc_asiu_div div; member
48 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
49 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
57 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
65 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_disable() local
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-regmap.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include "clk-regmap.h"
12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable() local
13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_endisable()
14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_regmap_gate_endisable()
18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled() local
35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_is_enabled()
38 regmap_read(clk->map, gate->offset, &val); in clk_regmap_gate_is_enabled()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/meson/ |
| D | clk-regmap.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include "clk-regmap.h"
12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable() local
13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_endisable()
14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_regmap_gate_endisable()
18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled() local
35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_is_enabled()
38 regmap_read(clk->map, gate->offset, &val); in clk_regmap_gate_is_enabled()
[all …]
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| D | clk-cpu-dyndiv.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-cpu-dyndiv.h"
14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data() argument
16 return (struct meson_clk_cpu_dyndiv_data *)clk->data; in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate() local
23 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); in meson_clk_cpu_dyndiv_recalc_rate()
26 meson_parm_read(clk->map, &data->div), in meson_clk_cpu_dyndiv_recalc_rate()
27 NULL, 0, data->div.width); in meson_clk_cpu_dyndiv_recalc_rate()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/spear/ |
| D | spear1340_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1340_clock.c
12 #include <linux/clk/spear.h>
16 #include "clk.h"
175 /* vco-pll4 rate configuration table, in ascending order of rates */
188 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
189 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
191 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
192 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/spear/ |
| D | spear1340_clock.c | 2 * arch/arm/mach-spear13xx/spear1340_clock.c
19 #include "clk.h"
178 /* vco-pll4 rate configuration table, in ascending order of rates */
191 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
193 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
194 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
195 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
196 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
208 * --------------------------------------------------------------------
[all …]
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| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| D | plldata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 struct clk clkin1 = {
127 struct clk c6x_core_clk = {
132 struct clk c6x_i2c_clk = {
136 struct clk c6x_watchdog_clk = {
140 struct clk c6x_mcbsp1_clk = {
144 struct clk c6x_mcbsp2_clk = {
148 struct clk c6x_mdio_clk = {
155 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
156 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mxs/ |
| D | clk-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/mxs/ |
| D | clk-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
[all …]
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| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
[all …]
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| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include "clk.h"
31 * src1 --|--\
32 * |M |--[GATE]-[DIV]-
33 * src2 --|--/
37 static struct clk *rockchip_clk_register_branch(const char *name, in rockchip_clk_register_branch()
[all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
13 #include "meson-mx-sdhc.h"
19 struct clk_divider div; member
34 { .div = 6, .val = 5, },
35 { .div = 8, .val = 7, },
36 { .div = 9, .val = 8, },
37 { .div = 10, .val = 9, },
38 { .div = 12, .val = 11, },
[all …]
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
13 #include "meson-mx-sdhc.h"
17 struct clk_divider div; member
32 { .div = 6, .val = 5, },
33 { .div = 8, .val = 7, },
34 { .div = 9, .val = 8, },
35 { .div = 10, .val = 9, },
36 { .div = 12, .val = 11, },
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
[all …]
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| D | clk-tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
21 #include "clk.h"
58 u32 val, div; in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
[all …]
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| D | clk-tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
20 #include "clk.h"
57 u32 val, div; in emc_recalc_rate() local
59 val = readl_relaxed(emc->reg); in emc_recalc_rate()
60 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include "../clk-fractional-divider.h"
26 #include "clk.h"
32 * src1 --|--\
33 * |M |--[GATE]-[DIV]-
34 * src2 --|--/
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-qoriq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
37 struct clk *clk; member
42 struct clockgen_pll_div div[MAX_PLL_DIV]; member
51 int div; /* PLL_DIVn */ member
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
89 struct clk *sysclk, *coreclk;
91 struct clk *cmux[NUM_CMUX];
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| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]
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