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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Drealtek,rtl82xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 realtek,clkout-disable:
24 Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset.
27 realtek,aldps-enable:
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
39 * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
40 * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
51 * enum si5351_drive_strength - Si5351 clock output drive strength
67 * enum si5351_disable_state - Si5351 clock output disable state
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/kernel/linux/linux-5.10/include/linux/platform_data/
Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
39 * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
40 * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
51 * enum si5351_drive_strength - Si5351 clock output drive strength
67 * enum si5351_disable_state - Si5351 clock output disable state
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/kernel/linux/linux-5.10/drivers/clk/
Dclk-si5351.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
63 struct si5351_hw_data *clkout; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
101 return regmap_bulk_read(drvdata->regmap, reg, buf, count); in si5351_bulk_read()
107 return regmap_write(drvdata->regmap, reg, val); in si5351_reg_write()
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Dclk-wm831x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2 Wolfson Microelectronics PLC.
10 #include <linux/clk-provider.h>
30 return clkdata->xtal_ena; in wm831x_xtal_is_prepared()
39 if (clkdata->xtal_ena) in wm831x_xtal_recalc_rate()
70 struct wm831x *wm831x = clkdata->wm831x; in wm831x_fll_is_prepared()
75 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n", in wm831x_fll_is_prepared()
87 struct wm831x *wm831x = clkdata->wm831x; in wm831x_fll_prepare()
93 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret); in wm831x_fll_prepare()
95 /* wait 2-3 ms for new frequency taking effect */ in wm831x_fll_prepare()
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/kernel/linux/linux-6.6/drivers/clk/
Dclk-si5351.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
10 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
12 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
63 struct si5351_hw_data *clkout; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
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Dclk-lmk04832.c1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
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Dclk-wm831x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2 Wolfson Microelectronics PLC.
10 #include <linux/clk-provider.h>
30 return clkdata->xtal_ena; in wm831x_xtal_is_prepared()
39 if (clkdata->xtal_ena) in wm831x_xtal_recalc_rate()
70 struct wm831x *wm831x = clkdata->wm831x; in wm831x_fll_is_prepared()
75 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n", in wm831x_fll_is_prepared()
87 struct wm831x *wm831x = clkdata->wm831x; in wm831x_fll_prepare()
93 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret); in wm831x_fll_prepare()
95 /* wait 2-3 ms for new frequency taking effect */ in wm831x_fll_prepare()
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/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
42 unsigned long fint, clkdco, clkout; in hdmi_pll_compute() local
47 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
49 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
56 n = DIV_ROUND_UP(clkin, hw->fint_max); in hdmi_pll_compute()
60 min_dco = roundup(hw->clkdco_min, fint); in hdmi_pll_compute()
71 if (WARN_ON(target_clkdco - clkdco > fint)) in hdmi_pll_compute()
74 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); in hdmi_pll_compute()
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/kernel/linux/linux-6.6/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
42 unsigned long fint, clkdco, clkout; in hdmi_pll_compute() local
47 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
49 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
56 n = DIV_ROUND_UP(clkin, hw->fint_max); in hdmi_pll_compute()
60 min_dco = roundup(hw->clkdco_min, fint); in hdmi_pll_compute()
71 if (WARN_ON(target_clkdco - clkdco > fint)) in hdmi_pll_compute()
74 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); in hdmi_pll_compute()
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/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
46 /* For fixed-factor ones */
133 D_ROOT(CLKOUT, "clkout", 25, 1),
135 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
136 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
137 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
138 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
139 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/
Dsja1000.txt5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
31 - nxp,tx-output-config : TX output pin configuration:
33 <0x02> : TX0 pull-down (default)
34 <0x04> : TX0 pull-up
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/kernel/linux/linux-6.6/drivers/clk/renesas/
Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
26 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
33 * struct regbit - describe one bit in a register
35 * expressed in units of 32-bit words (not bytes),
43 * Since registers are aligned on 32-bit boundaries, the
44 * offset will be specified in 32-bit words rather than bytes.
48 * offset from bytes to 32-bit words.
61 * struct r9a06g032_gate - clock-related control bits
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/omapdrm/dss/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
45 struct dss_device *dss = pll->dss; in dss_pll_unregister()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
45 struct dss_device *dss = pll->dss; in dss_pll_unregister()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nuvoton/
Dnuvoton-npcm750-pincfg-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 pin8_input: pin8-input {
8 bias-disable;
9 input-enable;
11 pin9_output_high: pin9-output-high {
13 bias-disable;
14 output-high;
16 pin10_input: pin10-input {
18 bias-disable;
19 input-enable;
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/kernel/linux/linux-6.6/drivers/clk/ti/
Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
181 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
182 "clock-output-names", in ti_adpll_clk_get_name()
188 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
189 d->pa, postfix); in ti_adpll_clk_get_name()
205 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
206 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
212 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
214 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
[all …]
/kernel/linux/linux-5.10/drivers/net/can/cc770/
Dcc770.c1 // SPDX-License-Identifier: GPL-2.0-only
43 * 2. Support of silent (listen-only) mode.
46 * Details are available from Bosch's "CC770_Product_Info_2007-01.pdf",
58 * "msgobj15_eff". If not equal 0, it will receive 29-bit EFF frames,
63 MODULE_PARM_DESC(msgobj15_eff, "Extended 29-bit frames for message object 15 "
64 "(default: 11-bit standard frames)");
102 return MSGOBJ_LAST + 2 - intid; in intid2obj()
112 for (o = 0; o < ARRAY_SIZE(priv->obj_flags); o++) { in enable_all_objs()
113 obj_flags = priv->obj_flags[o]; in enable_all_objs()
121 if (priv->control_normal_mode & CTRL_EAF) { in enable_all_objs()
[all …]
Dcc770.h1 /* SPDX-License-Identifier: GPL-2.0-only */
35 u8 clkout; /* Clock Out Register */ member
100 #define RXIE_RES 0x04 /* Receive Interrupt Disable */
103 #define TXIE_RES 0x10 /* Transmit Interrupt Disable */
141 priv->read_reg(priv, offsetof(struct cc770_regs, member))
144 priv->write_reg(priv, offsetof(struct cc770_regs, member), value)
162 #define obj2msgobj(o) (MSGOBJ_LAST - (o)) /* message object 11..15 */
171 /* the lower-layer is responsible for appropriate locking */
177 void *priv; /* for board-specific data */
186 u8 clkout; /* Clock out register */ member
/kernel/linux/linux-6.6/drivers/net/can/cc770/
Dcc770.c1 // SPDX-License-Identifier: GPL-2.0-only
44 * 2. Support of silent (listen-only) mode.
47 * Details are available from Bosch's "CC770_Product_Info_2007-01.pdf",
59 * "msgobj15_eff". If not equal 0, it will receive 29-bit EFF frames,
64 MODULE_PARM_DESC(msgobj15_eff, "Extended 29-bit frames for message object 15 "
65 "(default: 11-bit standard frames)");
103 return MSGOBJ_LAST + 2 - intid; in intid2obj()
113 for (o = 0; o < ARRAY_SIZE(priv->obj_flags); o++) { in enable_all_objs()
114 obj_flags = priv->obj_flags[o]; in enable_all_objs()
122 if (priv->control_normal_mode & CTRL_EAF) { in enable_all_objs()
[all …]
Dcc770.h1 /* SPDX-License-Identifier: GPL-2.0-only */
35 u8 clkout; /* Clock Out Register */ member
100 #define RXIE_RES 0x04 /* Receive Interrupt Disable */
103 #define TXIE_RES 0x10 /* Transmit Interrupt Disable */
141 priv->read_reg(priv, offsetof(struct cc770_regs, member))
144 priv->write_reg(priv, offsetof(struct cc770_regs, member), value)
162 #define obj2msgobj(o) (MSGOBJ_LAST - (o)) /* message object 11..15 */
171 /* the lower-layer is responsible for appropriate locking */
177 void *priv; /* for board-specific data */
186 u8 clkout; /* Clock out register */ member
/kernel/linux/linux-5.10/drivers/iio/adc/
Dstm32-dfsdm-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
20 #include "stm32-dfsdm.h"
88 unsigned int spi_clk_out_div; /* SPI clkout divider value */
105 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable()
106 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable()
109 ret = clk_prepare_enable(priv->aclk); in stm32_dfsdm_clk_prepare_enable()
111 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_prepare_enable()
120 if (priv->aclk) in stm32_dfsdm_clk_disable_unprepare()
121 clk_disable_unprepare(priv->aclk); in stm32_dfsdm_clk_disable_unprepare()
[all …]
/kernel/linux/linux-6.6/drivers/clk/ux500/
Dclk-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
38 return prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
45 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, in clk_prcmu_unprepare()
53 return prcmu_clock_rate(clk->cg_sel); in clk_prcmu_recalc_rate()
60 return prcmu_round_clock_rate(clk->cg_sel, rate); in clk_prcmu_round_rate()
67 return prcmu_set_clock_rate(clk->cg_sel, rate); in clk_prcmu_set_rate()
[all …]
/kernel/linux/linux-5.10/drivers/clk/ti/
Dadpll.c14 #include <linux/clk-provider.h>
190 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
191 "clock-output-names", in ti_adpll_clk_get_name()
197 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
198 d->pa, postfix); in ti_adpll_clk_get_name()
214 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
215 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
221 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
223 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
226 return -ENOMEM; in ti_adpll_setup_clock()
[all …]

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