| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-common.txt | 6 which generation the SoCs use:
7 generation 1: mt2701 and mt7623.
8 generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
10 There's slight differences between the two SMI, for generation 2, the
12 for generation 1, the register is at smi ao base(smi always on register
13 base). Besides that, the smi async clock should be prepared and enabled for
14 SMI generation 1 to transform the smi clock into emi clock domain, but that is
15 not needed for SMI generation 2.
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
17 which generation the SoCs use:
18 generation 1: mt2701 and mt7623.
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-scg-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
|
| D | imx8ulp-cgc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
10 - Jacky Bai <ping.bai@nxp.com>
13 On i.MX8ULP, The clock sources generation, distribution and management is
20 - fsl,imx8ulp-cgc1
21 - fsl,imx8ulp-cgc2
26 '#clock-cells':
[all …]
|
| D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
|
| D | imx8ulp-pcc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
10 - Jacky Bai <ping.bai@nxp.com>
13 On i.MX8ULP, The clock sources generation, distribution and management is
15 software reset, clock selection, optional division and clock gating mode
21 - fsl,imx8ulp-pcc3
22 - fsl,imx8ulp-pcc4
[all …]
|
| D | intel,cgu-lgm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU)
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
23 const: intel,cgu-lgm
28 '#clock-cells':
[all …]
|
| D | apple,nco.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apple,nco.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Povišer <povik+lin@cutebit.org>
14 such as the t8103 (M1) is a programmable clock generator performing
15 fractional division of a high frequency input clock.
18 generation of audio bitclocks.
23 - enum:
24 - apple,t6000-nco
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-scg-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
|
| D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
|
| D | intel,cgu-lgm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
23 const: intel,cgu-lgm
28 '#clock-cells':
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.txt | 4 this M4U have two generations of HW architecture. Generation one uses flat
5 pagetable, and only supports 4K size page mapping. Generation two uses the
6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
14 this M4U have two generations of HW architecture. Generation one uses flat
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/networking/dsa/ |
| D | sja1105.rst | 8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/ |
| D | ptp.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 /* Offset 0x01: Timestamp Clock Period (ps) */
36 /* Offset 0x02/0x03: Trigger Generation Amount */
40 /* Offset 0x04: Clock Compensation */
46 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
70 /* Offset 0x10/0x11: Trig Generation Time */
160 return -1; in mv88e6xxx_hwtstamp_work()
|
| /kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/ |
| D | ptp.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 /* Offset 0x01: Timestamp Clock Period (ps) */
36 /* Offset 0x02/0x03: Trigger Generation Amount */
40 /* Offset 0x04: Clock Compensation */
46 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
70 /* Offset 0x10/0x11: Trig Generation Time */
159 return -1; in mv88e6xxx_hwtstamp_work()
|
| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| D | clk-apbc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp APB clock operation source file
17 /* Common APB clock register bit definitions */
18 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
19 #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
20 #define APBC_RST (1 << 2) /* Reset Generation */
21 #define APBC_POWER (1 << 7) /* Reset Generation */
39 * It may share same register as MUX clock, in clk_apbc_prepare()
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-apbc.c | 2 * mmp APB clock operation source file
20 /* Common APB clock register bit definitions */
21 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
22 #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
23 #define APBC_RST (1 << 2) /* Reset Generation */
24 #define APBC_POWER (1 << 7) /* Reset Generation */
42 * It may share same register as MUX clock, in clk_apbc_prepare()
45 if (apbc->lock) in clk_apbc_prepare()
46 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
48 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | rcar-gen3-phy-pcie.txt | 1 * Renesas R-Car generation 3 PCIe PHY
3 This file provides information on what the device node for the R-Car
4 generation 3 PCIe PHY contains.
7 - compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the
9 - reg: offset and length of the register block.
10 - clocks: clock phandle and specifier pair.
11 - power-domains: power domain phandle and specifier pair.
12 - resets: reset phandle and specifier pair.
13 - #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
15 Example (R-Car V3H):
[all …]
|
| D | rcar-gen2-phy.txt | 1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
14 "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-mmp/ |
| D | regs-apbc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Application Peripheral Bus Clock Unit
9 #include "addr-map.h"
11 /* Common APB clock register bit definitions */
12 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
13 #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
14 #define APBC_RST (1 << 2) /* Reset Generation */
16 /* Functional Clock Selection Mask */
|
| /kernel/linux/linux-5.10/sound/firewire/digi00x/ |
| D | digi00x-stream.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * digi00x-stream.c - a part of driver for Digidesign Digi 002/003 family
5 * Copyright (c) 2014-2015 Takashi Sakamoto
36 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in snd_dg00x_stream_get_local_rate()
46 err = -EIO; in snd_dg00x_stream_get_local_rate()
61 return -EINVAL; in snd_dg00x_stream_set_local_rate()
64 return snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST, in snd_dg00x_stream_set_local_rate()
70 enum snd_dg00x_clock *clock) in snd_dg00x_stream_get_clock() argument
75 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in snd_dg00x_stream_get_clock()
81 *clock = be32_to_cpu(reg) & 0x0f; in snd_dg00x_stream_get_clock()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/networking/dsa/ |
| D | sja1105.rst | 10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
47 Clock Sync Params no no
56 Also the configuration is write-only (software cannot read it back from the
[all …]
|
| /kernel/linux/linux-6.6/sound/firewire/tascam/ |
| D | tascam-stream.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * tascam-stream.c - a part of driver for TASCAM FireWire series
23 err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST, in get_clock()
33 // In intermediate state after changing clock status. in get_clock()
39 return -EAGAIN; in get_clock()
45 enum snd_tscm_clock clock) in set_clock() argument
70 return -EAGAIN; in set_clock()
74 if (clock != INT_MAX) { in set_clock()
76 data |= clock + 1; in set_clock()
81 err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST, in set_clock()
[all …]
|
| /kernel/linux/linux-6.6/sound/firewire/digi00x/ |
| D | digi00x-stream.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * digi00x-stream.c - a part of driver for Digidesign Digi 002/003 family
5 * Copyright (c) 2014-2015 Takashi Sakamoto
36 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in snd_dg00x_stream_get_local_rate()
46 err = -EIO; in snd_dg00x_stream_get_local_rate()
61 return -EINVAL; in snd_dg00x_stream_set_local_rate()
64 return snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST, in snd_dg00x_stream_set_local_rate()
70 enum snd_dg00x_clock *clock) in snd_dg00x_stream_get_clock() argument
75 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in snd_dg00x_stream_get_clock()
81 *clock = be32_to_cpu(reg) & 0x0f; in snd_dg00x_stream_get_clock()
[all …]
|