| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | brcm,kona-ccu.txt | 4 clock control units (CCUs). A CCU is a clock provider that manages
5 a set of clock signals. Each CCU is represented by a node in the
8 This binding uses the common clock binding:
9 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
19 - reg
21 containing clock control registers
22 - #clock-cells
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | brcm,kona-ccu.txt | 4 clock control units (CCUs). A CCU is a clock provider that manages
5 a set of clock signals. Each CCU is represented by a node in the
8 This binding uses the common clock binding:
9 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
19 - reg
21 containing clock control registers
22 - #clock-cells
[all …]
|
| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (master mode only)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
23 #define CDNS_SPI_NAME "cdns-spi"
46 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
47 #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
51 #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
61 * SPI Configuration Register - Baud rate and slave select
102 * struct cdns_spi - This definition defines spi driver instance
[all …]
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| D | spi-jcore.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * J-Core SPI controller driver
5 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
36 struct spi_master *master; member
52 } while (--timeout); in jcore_spi_wait()
54 return -EBUSY; in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program()
62 dev_err(hw->master->dev.parent, in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
70 struct jcore_spi *hw = spi_master_get_devdata(spi->master); in jcore_spi_chipsel()
[all …]
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| D | spi-ppc4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
44 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
45 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
61 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
62 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
83 /* clock settings (SCP and CI) for various SPI modes */
[all …]
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| D | spi-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
26 #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
27 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
93 struct clk *clk; /* bus clock */
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
131 sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg) in sifive_spi_prepare_message() argument
[all …]
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| /kernel/linux/linux-5.10/sound/soc/sh/ |
| D | fsi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Fifo-attached Serial Interface (FSI) support for SH7724
12 #include <linux/dma-mapping.h>
42 /* master register */
102 #define SE (1 << 0) /* Fix the master clock */
166 * |<-------------------- period--------------------->|
169 * ||<----- frame ----->|<------ frame ----->| ... |
170 * |+--------------------+--------------------+- ... |
172 * |+--------------------+--------------------+- ... |
185 * --> go to codecs
[all …]
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| /kernel/linux/linux-6.6/sound/soc/sh/ |
| D | fsi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Fifo-attached Serial Interface (FSI) support for SH7724
12 #include <linux/dma-mapping.h>
42 /* master register */
102 #define SE (1 << 0) /* Fix the master clock */
166 * |<-------------------- period--------------------->|
169 * ||<----- frame ----->|<------ frame ----->| ... |
170 * |+--------------------+--------------------+- ... |
172 * |+--------------------+--------------------+- ... |
185 * --> go to codecs
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
[all …]
|
| /kernel/linux/linux-6.6/Documentation/sound/soc/ |
| D | clocking.rst | 9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
14 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
24 The Digital Audio Interface is usually driven by a Bit Clock (often referred to
25 as BCLK). This clock is used to drive the digital audio data across the link
[all …]
|
| /kernel/linux/linux-5.10/Documentation/sound/soc/ |
| D | clocking.rst | 9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
14 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
24 The Digital Audio Interface is usually driven by a Bit Clock (often referred to
25 as BCLK). This clock is used to drive the digital audio data across the link
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
16 $ref: /schemas/types.yaml#/definitions/phandle-array
19 bitclock-master:
20 description: Indicates dai-link bit clock master
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.txt | 3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/ |
| D | cortina,gemini-sata-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
31 - const: sata1
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/i3c/ |
| D | silvaco,i3c-master.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silvaco I3C master
10 - Conor Culhane <conor.culhane@silvaco.com>
13 - $ref: i3c.yaml#
17 const: silvaco,i3c-master-v1
27 - description: system clock
28 - description: bus clock
[all …]
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| /kernel/linux/linux-5.10/include/linux/soundwire/ |
| D | sdw.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 /* SDW Master Device Number, not supported yet */
71 * enum sdw_slave_status - Slave status
85 * enum sdw_clk_stop_type: clock stop operations
87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
88 * @SDW_CLK_POST_PREPARE: post clock stop prepare
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
[all …]
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| /kernel/linux/linux-5.10/sound/soc/mxs/ |
| D | mxs-saif.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/dma-mapping.h>
14 #include <linux/clk-provider.h>
23 #include "mxs-saif.h"
31 * SAIF is a little different with other normal SOC DAIs on clock using.
33 * For MXS, two SAIF modules are instantiated on-chip.
34 * Each SAIF has a set of clock pins and can be operating in master
35 * mode simultaneously if they are connected to different off-chip codecs.
36 * Also, one of the two SAIFs can master or drive the clock pins while the
37 * other SAIF, in slave mode, receives clocking from the master SAIF.
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/mxs/ |
| D | mxs-saif.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/dma-mapping.h>
14 #include <linux/clk-provider.h>
23 #include "mxs-saif.h"
31 * SAIF is a little different with other normal SOC DAIs on clock using.
33 * For MXS, two SAIF modules are instantiated on-chip.
34 * Each SAIF has a set of clock pins and can be operating in master
35 * mode simultaneously if they are connected to different off-chip codecs.
36 * Also, one of the two SAIFs can master or drive the clock pins while the
37 * other SAIF, in slave mode, receives clocking from the master SAIF.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/spi/ |
| D | spi-summary.rst | 5 02-Feb-2012
8 ------------
12 standardization body. SPI uses a master/slave configuration.
14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
18 commonly used. Each clock cycle shifts data out and data in; the clock
26 other signals, often including an interrupt to the master.
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
[all …]
|
| /kernel/linux/linux-5.10/Documentation/spi/ |
| D | spi-summary.rst | 5 02-Feb-2012
8 ------------
12 standardization body. SPI uses a master/slave configuration.
14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
18 commonly used. Each clock cycle shifts data out and data in; the clock
26 other signals, often including an interrupt to the master.
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
[all …]
|
| /kernel/linux/linux-5.10/Documentation/driver-api/soundwire/ |
| D | summary.rst | 10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
17 (2) Lower clock frequency, and hence lower power consumption, by use of DDR
20 (3) Clock scaling and optional multiple data lanes to give wide flexibility
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
26 interfaces share the common Bus containing data and clock line. Each of the
35 Below figure shows an example of connectivity between a SoundWire Master and
38 +---------------+ +---------------+
39 | | Clock Signal | |
40 | Master |-------+-------------------------------| Slave |
[all …]
|
| /kernel/linux/linux-6.6/Documentation/driver-api/soundwire/ |
| D | summary.rst | 10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
17 (2) Lower clock frequency, and hence lower power consumption, by use of DDR
20 (3) Clock scaling and optional multiple data lanes to give wide flexibility
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
26 interfaces share the common Bus containing data and clock line. Each of the
35 Below figure shows an example of connectivity between a SoundWire Master and
38 +---------------+ +---------------+
39 | | Clock Signal | |
40 | Master |-------+-------------------------------| Slave |
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/atmel/ |
| D | atmel-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 * ---- I2S Controller Register map ----
44 * ---- Control Register (Write-only) ----
48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
55 * ---- Mode Register (Read/Write) ----
101 /* Audio Clock to I2SC Master Clock ratio */
106 /* Master Clock to fs ratio */
111 /* Master Clock mode */
113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
[all …]
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| /kernel/linux/linux-6.6/sound/soc/atmel/ |
| D | atmel-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 * ---- I2S Controller Register map ----
44 * ---- Control Register (Write-only) ----
48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
55 * ---- Mode Register (Read/Write) ----
101 /* Audio Clock to I2SC Master Clock ratio */
106 /* Master Clock to fs ratio */
111 /* Master Clock mode */
113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
[all …]
|