| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| D | samsung,exynos-ext-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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| D | samsung,s5pv210-audss-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5Pv210 SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
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| D | samsung,exynos5410-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5410 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| D | samsung,exynos5433-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos5433-clock.txt | 1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
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| D | clk-s5pv210-audss.txt | 1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
17 a clock named "xxti".
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
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| D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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| D | exynos5410-clock.txt | 1 * Samsung Exynos5410 Clock Controller
3 The Exynos5410 clock controller generates and supplies clock to various
8 - compatible: should be "samsung,exynos5410-clock"
10 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
15 - clocks: should contain an entry specifying the root clock from external
16 oscillator supplied through XXTI or XusbXTI pin. This clock should be
17 defined using standard clock bindings with "fin_pll" clock-output-name.
18 That clock is being passed internally to the 9 PLLs.
21 dt-bindings/clock/exynos5410.h header and can be used in device
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| D | exynos7-clock.txt | 1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/ |
| D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
36 compatible = "arm,cortex-a57-pmu";
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/ |
| D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/ |
| D | s5pv210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a8";
55 xxti: oscillator-0 { label
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| D | exynos4412-tiny4412.dts | 1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
25 stdout-path = &serial_0;
34 compatible = "gpio-leds";
40 default-state = "off";
41 linux,default-trigger = "heartbeat";
47 default-state = "off";
53 default-state = "off";
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| D | exynos4412-smdk4412.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include "exynos-mfc-reserved-memory.dtsi"
31 stdout-path = "serial1:115200n8";
34 fixed-rate-clocks {
35 xxti {
36 compatible = "samsung,clock-xxti";
37 clock-frequency = <0>;
41 compatible = "samsung,clock-xusbxti";
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| D | exynos4210-smdkv310.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include "exynos-mfc-reserved-memory.dtsi"
34 stdout-path = "serial1:115200n8";
37 fixed-rate-clocks {
38 xxti {
39 compatible = "samsung,clock-xxti";
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos4412-tiny4412.dts | 1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
20 stdout-path = &serial_0;
29 compatible = "gpio-leds";
34 default-state = "off";
35 linux,default-trigger = "heartbeat";
41 default-state = "off";
47 default-state = "off";
53 default-state = "off";
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| D | s5pv210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a8";
55 xxti: oscillator-0 { label
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| D | exynos4412-smdk4412.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include "exynos-mfc-reserved-memory.dtsi"
27 stdout-path = "serial1:115200n8";
30 fixed-rate-clocks {
31 xxti {
32 compatible = "samsung,clock-xxti";
33 clock-frequency = <0>;
37 compatible = "samsung,clock-xusbxti";
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| D | exynos4210-smdkv310.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include "exynos-mfc-reserved-memory.dtsi"
30 stdout-path = "serial1:115200n8";
33 fixed-rate-clocks {
34 xxti {
35 compatible = "samsung,clock-xxti";
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-s5pv210-audss.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on Exynos Audio Subsystem Clock Controller driver:
10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
15 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/s5pv210-audss.h>
74 reg_base = devm_ioremap_resource(&pdev->dev, res); in s5pv210_audss_clk_probe()
76 dev_err(&pdev->dev, "failed to map audss registers\n"); in s5pv210_audss_clk_probe()
80 clk_data = devm_kzalloc(&pdev->dev, in s5pv210_audss_clk_probe()
85 return -ENOMEM; in s5pv210_audss_clk_probe()
87 clk_data->num = AUDSS_MAX_CLKS; in s5pv210_audss_clk_probe()
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| D | clk-s5pv210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Based on clock drivers for S3C64xx and Exynos4 SoCs.
8 * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
11 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
18 #include <dt-bindings/clock/s5pv210.h>
20 /* S5PC110/S5PV210 clock controller register offsets */
76 xxti, enumerator
130 "xxti",
167 "xxti",
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-s5pv210-audss.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on Exynos Audio Subsystem Clock Controller driver:
10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
15 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/s5pv210-audss.h>
76 clk_data = devm_kzalloc(&pdev->dev, in s5pv210_audss_clk_probe()
81 return -ENOMEM; in s5pv210_audss_clk_probe()
83 clk_data->num = AUDSS_MAX_CLKS; in s5pv210_audss_clk_probe()
84 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
86 hclk = devm_clk_get(&pdev->dev, "hclk"); in s5pv210_audss_clk_probe()
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| D | clk-s5pv210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Based on clock drivers for S3C64xx and Exynos4 SoCs.
8 * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
11 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
18 #include <dt-bindings/clock/s5pv210.h>
20 /* S5PC110/S5PV210 clock controller register offsets */
76 xxti, enumerator
130 "xxti",
167 "xxti",
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| D | clk-exynos4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Common Clock Framework support for all Exynos4 SoCs.
10 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
21 /* Exynos4 clock controller register offsets */
138 /* NOTE: Must be equal to the last clock ID increased by one */
282 /* list of all parent clock list */
299 /* Exynos 4210-specific parent groups */
303 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
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