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/third_party/mesa3d/src/gallium/drivers/llvmpipe/ci/
Dgitlab-ci.yml1 .llvmpipe-test:
3 - .llvmpipe-rules
7 FLAKES_CHANNEL: "#mesa-swrast-ci"
10 llvmpipe-piglit-cl:
12 - .test-cl
13 - .piglit-test
14 - .llvmpipe-test
15 - .llvmpipe-cl-rules
20 PIGLIT_RESULTS: "llvmpipe-cl"
22 -x bswap -x phatk -x clz-optimizations
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/third_party/mesa3d/src/panfrost/bifrost/
Dbifrost_compile.c52 {"inorder", BIFROST_DBG_INORDER, "Force in-order bundling"},
80 if (bi_is_null(b->shader->preloaded[reg])) { in bi_preload()
83 b_.cursor = bi_before_block(bi_start_block(&b->shader->blocks)); in bi_preload()
86 b->shader->preloaded[reg] = bi_mov_i32(&b_, bi_register(reg)); in bi_preload()
89 return b->shader->preloaded[reg]; in bi_preload()
95 if (bi_is_null(b->shader->coverage)) in bi_coverage()
96 b->shader->coverage = bi_preload(b, 60); in bi_coverage()
98 return b->shader->coverage; in bi_coverage()
109 return bi_preload(b, (b->shader->arch >= 9) ? 60 : 61); in bi_vertex_id()
115 return bi_preload(b, (b->shader->arch >= 9) ? 61 : 62); in bi_instance_id()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DREADME.txt1 //===---------------------------------------------------------------------===//
3 //===---------------------------------------------------------------------===//
8 add doesn't need to overflow between the two 16-bit chunks.
15 Interesting optimization for PIC codegen on arm-linux:
18 //===---------------------------------------------------------------------===//
20 Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the
21 time regalloc happens, these values are now in a 32-bit register, usually with
22 the top-bits known to be sign or zero extended. If spilled, we should be able
23 to spill these to a 8-bit or 16-bit stack slot, zero or sign extending as part
30 //===---------------------------------------------------------------------===//
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DARMISelLowering.cpp1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
119 #define DEBUG_TYPE "arm-isel"
128 ARMInterworking("arm-interworking", cl::Hidden,
133 "arm-promote-constant", cl::Hidden,
138 "arm-promote-constant-max-size", cl::Hidden,
142 "arm-promote-constant-max-total", cl::Hidden,
147 MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
69 #define DEBUG_TYPE "ppc-codegen"
82 "Number of compares not eliminated as they have non-extending uses.");
87 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
91 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
95 "ppc-bit-perm-rewriter-stress-rotates",
101 "ppc-use-branch-hint", cl::init(true),
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/third_party/mesa3d/src/panfrost/bifrost/valhall/
DISA.xml1 <!--
22 -->
31 separate half-words and individual bytes via swizzles on the source.
34 <constant desc="All ones; integer $-1$">0xFFFFFFFF</constant>
35 <constant desc="Maximum integer; floating-point NaN">0x7FFFFFFF</constant>
36 <constant desc="Integers $(-2, -3, -4, -5)$">0xFAFCFDFE</constant>
37 <constant desc="16-bit integer $2^8$">0x01000000</constant>
55 <constant desc="Float $65535.0 = 2^{16} - 1$">0x477FFF00</constant>
56 <constant desc="Half-float $(255.0, 256.0) = (2^8 - 1, 2^8)$">0x5C005BF8</constant>
57 <constant desc="Half-float $0.1 = 1 / 10$">0x2E660000</constant>
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/third_party/skia/third_party/externals/libwebp/
DChangeLog3 731246ba update ChangeLog (tag: v1.2.1-rc2)
10 ece18e55 dsp.h: respect --disable-sse2/sse4.1/neon
56 98bbe35b Fix multi-threading with palettes.
63 8fdaecb0 Disable cross-color when palette is used.
77 fee64287 Merge "wicdec,icc: treat unsupported op as non-fatal"
79 b27ea852 wicdec,icc: treat unsupported op as non-fatal
82 a8853394 SSE4.1 versions of BGRA to RGB/BGR color-space conversions
88 373eb170 gif2webp: don't store loop-count if there's only 1 frame
95 fedac6cc update ChangeLog (tag: v1.2.0-rc3, tag: v1.2.0)
113 2e7bed79 WebPPicture: clarify the ownership of user-owned data.
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/third_party/mesa3d/docs/relnotes/
D20.0.0.rst1 Mesa 20.0.0 Release Notes / 2020-02-19
21 ---------------
25 bb6db3e54b608d2536d4000b3de7dd3ae115fc114e8acbb5afff4b3bbed04b34 mesa-20.0.0.tar.xz
28 ------------
30 - OpenGL 4.6 on radeonsi.
31 - GL_ARB_gl_spirv on radeonsi.
32 - GL_ARB_spirv_extensions on radeonsi.
33 - GL_EXT_direct_state_access for compatibility profile.
34 - VK_AMD_device_coherent_memory on RADV.
35 - VK_AMD_mixed_attachment_samples on RADV.
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D22.2.0.rst1 Mesa 22.2.0 Release Notes / 2022-09-21
20 ---------------
24 b1f9c8fd08f2cae3adf83355bef4d2398e8025f44947332880f2d0066bdafa8c mesa-22.2.0.tar.xz
29 ------------
31 - WGL_ARB_create_context_robustness
33 - d3d12 ARB_robust_buffer_access_behavior
35 - VK_EXT_robustness2 for lavapipe
37 - VK_EXT_image_2d_view_of_3d on RADV
39 - zink and d3d12 GL_EXT_memory_object_win32 and GL_EXT_semaphore_win32 support
41 - vertexAttributeInstanceRateZeroDivisor support for lavapipe
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
38 #define DEBUG_TYPE "wasm-lower"
43 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
53 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
59 if (Subtarget->hasSIMD128()) { in WebAssemblyTargetLowering()
65 if (Subtarget->hasUnimplementedSIMD128()) { in WebAssemblyTargetLowering()
70 computeRegisterProperties(Subtarget->getRegisterInfo()); in WebAssemblyTargetLowering()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
81 #define DEBUG_TYPE "mips-lower"
86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
146 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); in getGlobalReg()
152 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); in getTargetNode()
158 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); in getTargetNode()
164 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); in getTargetNode()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/
DREADME.txt3 //===---------------------------------------------------------------------===//
14 The legalization code for mul-with-overflow needs to be made more robust before
17 //===---------------------------------------------------------------------===//
19 Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and
25 //===---------------------------------------------------------------------===//
27 On targets with expensive 64-bit multiply, we could LSR this:
39 //===---------------------------------------------------------------------===//
41 Shrink: (setlt (loadi32 P), 0) -> (setlt (loadi8 Phi), 0)
43 //===---------------------------------------------------------------------===//
57 //===---------------------------------------------------------------------===//
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
DSimplifyCFG.cpp1 //===- SimplifyCFG.cpp - Code to perform CFG simplification ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
94 "phi-node-folding-threshold", cl::Hidden, cl::init(2),
99 "two-entry-phi-node-folding-threshold", cl::Hidden, cl::init(4),
101 "to speculatively execute to fold a 2-entry PHI node into a "
105 "simplifycfg-dup-ret", cl::Hidden, cl::init(false),
109 SinkCommon("simplifycfg-sink-common", cl::Hidden, cl::init(true),
113 "simplifycfg-hoist-cond-stores", cl::Hidden, cl::init(true),
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
54 return VT.getSizeInBits() - Known.countMinLeadingZeros(); in numBitsUnsigned()
60 // In order for this to be a signed 24-bit value, bit 23, must in numBitsSigned()
62 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op); in numBitsSigned()
106 // There are no 64-bit extloads. These should be done as a 32-bit extload and in AMDGPUTargetLowering()
107 // an extension to 64-bit. in AMDGPUTargetLowering()
332 // The hardware supports 32-bit ROTR, but not ROTL. in AMDGPUTargetLowering()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
56 if (F.getFnAttribute("disable-tail-calls").getValueAsString() == "true") in isInTailCallPosition()
92 // for the function live-in value of register Reg) in parametersInCSRMatch()
94 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
96 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); in parametersInCSRMatch()
107 IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt); in setAttributes()
108 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTargetLoweringARM32.cpp1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
8 //===----------------------------------------------------------------------===//
12 /// entirely of the lowering sequence for each high-level instruction.
14 //===----------------------------------------------------------------------===//
74 /// C++ 14 -- which defines constexpr members to std::initializer_list.
150 // In some cases, there are x-macros tables for both high-level and low-level
159 // Define a temporary set of enum values based on low-level table entries.
167 // Define a set of constants based on high-level table entries.
172 // Define a set of constants based on low-level table entries, and ensure the
180 // Repeat the static asserts with respect to the high-level table entries in
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/third_party/skia/third_party/externals/wuffs/release/c/
Dwuffs-v0.3.c7 // To use that single file as a "foo.c"-like implementation, instead of a
8 // "foo.h"-like header, #define WUFFS_IMPLEMENTATION before #include'ing or
11 // Wuffs' C code is generated automatically, not hand-written. These warnings'
15 // __GNUC__, clang-cl (which mimics MSVC's cl.exe) does not.
18 #pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
19 #pragma GCC diagnostic ignored "-Wmissing-field-initializers"
20 #pragma GCC diagnostic ignored "-Wunreachable-code"
21 #pragma GCC diagnostic ignored "-Wunused-function"
22 #pragma GCC diagnostic ignored "-Wunused-parameter"
24 #pragma GCC diagnostic ignored "-Wold-style-cast"
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/third_party/astc-encoder/Source/
Dwuffs-v0.3.c7 // To use that single file as a "foo.c"-like implementation, instead of a
8 // "foo.h"-like header, #define WUFFS_IMPLEMENTATION before #include'ing or
11 // Wuffs' C code is generated automatically, not hand-written. These warnings'
15 // __GNUC__, clang-cl (which mimics MSVC's cl.exe) does not.
18 #pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
19 #pragma GCC diagnostic ignored "-Wmissing-field-initializers"
20 #pragma GCC diagnostic ignored "-Wunreachable-code"
21 #pragma GCC diagnostic ignored "-Wunused-function"
22 #pragma GCC diagnostic ignored "-Wunused-parameter"
24 #pragma GCC diagnostic ignored "-Wold-style-cast"
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/third_party/mesa3d/
D.pick_status.json31 "description": "pps: make pps-producer RT only on freedreno",
58 …"description": "tree-wide: Convert all usage of PIPE_(OS|ARCH|CC)_* to DETECT_(OS|ARCH|CC)_* by us…
67 …"description": "tree-wide: Convert all usage of #ifndef PIPE_(OS|ARCH|CC)_* to #if DETECT_(OS|ARCH…
76 …"description": "tree-wide: Convert all usage of #ifdef PIPE_(OS|ARCH|CC)_* to #if DETECT_(OS|ARCH|…
85 …"description": "tree-wide: Convert all usage of defined PIPE_(OS|ARCH|CC)_* to DETECT_(OS|ARCH|CC)…
94 …"description": "tree-wide: Convert all usage of defined(PIPE_(OS|ARCH|CC)_*) to DETECT_(OS|ARCH|CC…
220 …"description": "mesa/vbo: Replace the usage of cpu_has_sse4_1 with util_get_cpu_caps()->has_sse4_1…
256 "description": "microsoft/compiler: Delete now-unused memcpy lowering pass",
436 "description": "docs: fix badly encoded envvar-roles",
454 "description": "docs: remove stale envvar-reference",
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
66 #define DEBUG_TYPE "x86-isel"
71 "x86-experimental-pref-loop-alignment", cl::init(4),
74 "(the last x86-experimental-pref-loop-alignment bits"
80 "x86-enable-old-knl-abi", cl::init(false),
86 "mul-constant-optimization", cl::init(true),
92 "x86-experimental-unordered-atomic-isel", cl::init(false),
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