| /kernel/linux/linux-6.6/drivers/thermal/intel/ |
| D | intel_tcc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
12 * intel_tcc_get_tjmax() - returns the default TCC activation Temperature
13 * @cpu: cpu that the MSR should be run on, nagative value means any cpu.
20 int intel_tcc_get_tjmax(int cpu) in intel_tcc_get_tjmax() argument
25 if (cpu < 0) in intel_tcc_get_tjmax()
28 err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_tjmax()
34 return val ? val : -ENODATA; in intel_tcc_get_tjmax()
39 * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax
40 * @cpu: cpu that the MSR should be run on, nagative value means any cpu.
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/rseq/ |
| D | param_test.c | 1 // SPDX-License-Identifier: LGPL-2.1
44 static __thread __attribute__((tls_model("initial-exec")))
49 static __thread __attribute__((tls_model("initial-exec"), unused))
113 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
204 "addiu " INJECT_ASM_REG ", -1\n\t" \
226 "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
245 if (loc_nr_loops == -1 && opt_modulo) { \
246 if (yield_mod_cnt == opt_modulo - 1) { \
297 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
317 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
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| /kernel/linux/linux-5.10/tools/testing/selftests/rseq/ |
| D | param_test.c | 1 // SPDX-License-Identifier: LGPL-2.1
47 static __thread __attribute__((tls_model("initial-exec")))
52 static __thread __attribute__((tls_model("initial-exec"), unused))
116 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
207 "addiu " INJECT_ASM_REG ", -1\n\t" \
225 if (loc_nr_loops == -1 && opt_modulo) { \
226 if (yield_mod_cnt == opt_modulo - 1) { \
301 intptr_t offset; member
318 intptr_t offset; member
327 /* A simple percpu spinlock. Grabs lock on current cpu. */
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| /kernel/linux/linux-5.10/arch/arm/mach-zynq/ |
| D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
41 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
43 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
47 * zynq_slcr_read - Read a register in SLCR block
50 * @offset: Register offset in SLCR block
54 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-zynq/ |
| D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
41 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
43 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
47 * zynq_slcr_read - Read a register in SLCR block
50 * @offset: Register offset in SLCR block
54 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
[all …]
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| /kernel/linux/linux-6.6/Documentation/core-api/ |
| D | this_cpu_ops.rst | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
65 ------------------------------------
[all …]
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | this_cpu_ops.rst | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
66 ------------------------------------
[all …]
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-mvebu.c | 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
29 * - the armadaxp variant for Armada XP systems. This variant keeps
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
[all …]
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| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * - the armadaxp variant for Armada XP systems. This variant keeps
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
77 /* The MV78200 has per-CPU registers for edge mask and level mask */
[all …]
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| /kernel/linux/linux-5.10/arch/loongarch/kvm/intc/ |
| D | ls3a_ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
11 #define ls3a_gipi_lock(s, flags) spin_lock_irqsave(&s->lock, flags)
12 #define ls3a_gipi_unlock(s, flags) spin_unlock_irqrestore(&s->lock, flags)
16 int kvm_helper_send_ipi(struct kvm_vcpu *vcpu, unsigned int cpu, unsigned int action) in kvm_helper_send_ipi() argument
18 struct kvm *kvm = vcpu->kvm; in kvm_helper_send_ipi()
20 gipiState *s = &(ipi->ls3a_gipistate); in kvm_helper_send_ipi()
24 kvm->stat.pip_write_exits++; in kvm_helper_send_ipi()
27 if (s->core[cpu].status == 0) { in kvm_helper_send_ipi()
28 irq.cpu = cpu; in kvm_helper_send_ipi()
[all …]
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| /kernel/linux/linux-5.10/arch/ia64/include/asm/uv/ |
| D | uv_hub.h | 23 * M - The low M bits of a physical address represent the offset
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
34 * right shift the NASID by 1 to exclude the always-zero bit.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * +--------------------------------+---------------------+
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
[all …]
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| /kernel/linux/linux-6.6/arch/ia64/include/asm/uv/ |
| D | uv_hub.h | 23 * M - The low M bits of a physical address represent the offset
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
34 * right shift the NASID by 1 to exclude the always-zero bit.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * +--------------------------------+---------------------+
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
[all …]
|
| /kernel/linux/linux-6.6/kernel/time/ |
| D | timer_list.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
49 SEQ_printf(m, " #%d: <%pK>, %ps", idx, taddr, timer->function); in print_timer()
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
[all …]
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| /kernel/linux/linux-6.6/arch/x86/include/asm/uv/ |
| D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/include/asm/uv/ |
| D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
22 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
37 cpu = map + offset_in_page(offset); in cpu_set()
40 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
42 *cpu = v; in cpu_set()
45 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
28 u32 *cpu; in cpu_set() local
31 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
32 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
36 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
38 cpu = map + offset_in_page(offset); in cpu_set()
41 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
43 *cpu = v; in cpu_set()
46 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
[all …]
|
| /kernel/linux/linux-6.6/tools/testing/selftests/kvm/lib/aarch64/ |
| D | gic_v3.c | 1 // SPDX-License-Identifier: GPL-2.0
39 GUEST_ASSERT(count--); in gicv3_gicd_wait_for_rwp()
49 GUEST_ASSERT(count--); in gicv3_gicr_wait_for_rwp()
109 * All other fields are read-only, so no need to read CTLR first. In in gicv3_set_eoi_split()
117 uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset) in gicv3_reg_readl() argument
121 return readl(base + offset); in gicv3_reg_readl()
124 void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val) in gicv3_reg_writel() argument
128 writel(reg_val, base + offset); in gicv3_reg_writel()
131 uint32_t gicv3_getl_fields(uint32_t cpu_or_dist, uint64_t offset, uint32_t mask) in gicv3_getl_fields() argument
133 return gicv3_reg_readl(cpu_or_dist, offset) & mask; in gicv3_getl_fields()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | krait-cc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
54 mux->reparent = false; in krait_notifier_cb()
61 if (!mux->reparent) in krait_notifier_cb()
62 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
63 mux->old_index); in krait_notifier_cb()
74 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
[all …]
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| /kernel/linux/linux-5.10/kernel/time/ |
| D | timer_list.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
62 print_name_offset(m, timer->function); in print_timer()
63 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
65 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
68 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
69 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
86 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | krait-cc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
42 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
43 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
44 mux->reparent = false; in krait_notifier_cb()
51 if (!mux->reparent) in krait_notifier_cb()
52 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
53 mux->old_index); in krait_notifier_cb()
64 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/lima/ |
| D | lima_vm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/lima/ |
| D | lima_vm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
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| /kernel/linux/linux-5.10/drivers/oprofile/ |
| D | buffer_sync.c | 4 * @remark Copyright 2002-2009 OProfile authors
12 * CPU buffer is processed and entered into the
17 * transitory EIP value into a persistent dentry/offset
20 * See fs/dcookies.c for a description of the dentry/offset
62 list_add(&task->tasks, &dying_tasks); in task_free_notify()
74 /* To avoid latency problems, we only process the current CPU, in task_exit_notify()
75 * hoping that most samples for the task are on this CPU in task_exit_notify()
91 struct mm_struct *mm = current->mm; in munmap_notify()
97 if (mpnt && mpnt->vm_file && (mpnt->vm_flags & VM_EXEC)) { in munmap_notify()
99 /* To avoid latency problems, we only process the current CPU, in munmap_notify()
[all …]
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| /kernel/liteos_a/arch/arm/gic/ |
| D | gic_v3.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
45 return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) | /* 3: Serial number, 32: Register bit offset */ in MpidrToAffinity()
46 (MPIDR_AFF_LEVEL(mpidr, 2) << 16) | /* 2: Serial number, 16: Register bit offset */ in MpidrToAffinity()
47 (MPIDR_AFF_LEVEL(mpidr, 1) << 8) | /* 1: Serial number, 8: Register bit offset */ in MpidrToAffinity()
53 STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask) in NextCpu() argument
55 UINT32 next = cpu + 1; in NextCpu()
73 UINT32 cpu = *base; in GicTargetList() local
74 UINT64 mpidr = CPU_MAP_GET(cpu); in GicTargetList()
75 while (cpu < LOSCFG_KERNEL_CORE_NUM) { in GicTargetList()
[all …]
|