Home
last modified time | relevance | path

Searched +full:ddr +full:- +full:config (Results 1 – 25 of 417) sorted by relevance

12345678910>>...17

/kernel/linux/linux-5.10/drivers/memory/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
25 config ARM_PL172_MPMC
33 config ATMEL_SDRAMC
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
[all …]
/kernel/linux/linux-6.6/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 config ARM_CCI_PMU
17 If compiled as a module, it will be called arm-cci.
19 config ARM_CCI400_PMU
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
28 config ARM_CCI5xx_PMU
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
37 config ARM_CCN
[all …]
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
50 /* DDR Perf hardware feature */
55 unsigned int quirks; /* quirks needed for different DDR Perf core */
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
91 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
116 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
[all …]
/kernel/linux/linux-6.6/drivers/memory/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
25 config ARM_PL172_MPMC
33 config ATMEL_EBI
42 Used to configure the EBI (external bus interface) when the device-
46 config BRCMSTB_DPFE
52 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
[all …]
Dbrcmstb_memc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
38 void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG; in brcmstb_memc_uses_lpddr4() local
41 reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK; in brcmstb_memc_uses_lpddr4()
49 void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset; in brcmstb_memc_srpd_config()
54 return -EINVAL; in brcmstb_memc_srpd_config()
56 memc->timeout_cycles = cycles; in brcmstb_memc_srpd_config()
74 return sprintf(buf, "%d\n", memc->frequency); in frequency_show()
82 return sprintf(buf, "%d\n", memc->timeout_cycles); in srpd_show()
98 return -EOPNOTSUPP; in srpd_store()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
[all …]
/kernel/linux/linux-6.6/drivers/regulator/
Dbd9571mwv-regulator.c1 // SPDX-License-Identifier: GPL-2.0
3 * ROHM BD9571MWV-M and BD9574MWF-M regulator driver
12 #include <linux/mfd/rohm-generic.h>
23 /* DDR Backup Power */
24 u8 bkup_mode_cnt_keepon; /* from "rohm,ddr-backup-power" */
57 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_SET_MONI, &val); in bd9571mwv_avs_get_moni_state()
73 return regmap_write_bits(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), in bd9571mwv_avs_set_voltage_sel_regmap()
74 rdev->desc->vsel_mask, sel); in bd9571mwv_avs_set_voltage_sel_regmap()
86 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), &val); in bd9571mwv_avs_get_voltage_sel_regmap()
90 val &= rdev->desc->vsel_mask; in bd9571mwv_avs_get_voltage_sel_regmap()
[all …]
/kernel/linux/linux-6.6/drivers/edac/
DKconfig6 config EDAC_ATOMIC_SCRUB
9 config EDAC_SUPPORT
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
34 config EDAC_DEBUG
40 levels are 0-4 (from low to high) and by default it is set to 2.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
[all …]
/kernel/linux/linux-5.10/drivers/regulator/
Dbd9571mwv-regulator.c1 // SPDX-License-Identifier: GPL-2.0
3 * ROHM BD9571MWV-M regulator driver
22 /* DDR Backup Power */
23 u8 bkup_mode_cnt_keepon; /* from "rohm,ddr-backup-power" */
56 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_SET_MONI, &val); in bd9571mwv_avs_get_moni_state()
72 return regmap_write_bits(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), in bd9571mwv_avs_set_voltage_sel_regmap()
73 rdev->desc->vsel_mask, sel); in bd9571mwv_avs_set_voltage_sel_regmap()
85 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), &val); in bd9571mwv_avs_get_voltage_sel_regmap()
89 val &= rdev->desc->vsel_mask; in bd9571mwv_avs_get_voltage_sel_regmap()
90 val >>= ffs(rdev->desc->vsel_mask) - 1; in bd9571mwv_avs_get_voltage_sel_regmap()
[all …]
/kernel/linux/linux-6.6/sound/soc/sprd/
Dsprd-pcm-compress.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/dma-mapping.h>
6 #include <linux/dma/sprd-dma.h>
14 #include "sprd-pcm-dma.h"
31 #define SPRD_COMPR_IRAM_LINKLIST_SIZE (1024 - SPRD_COMPR_IRAM_INFO_SIZE)
36 /* Stage 1 DDR buffer size definition */
52 * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59 * power-on) and DDR buffer. The source channel will transfer data from IRAM
62 * DDR buffer to IRAM buffer.
[all …]
/kernel/linux/linux-5.10/sound/soc/sprd/
Dsprd-pcm-compress.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/dma-mapping.h>
6 #include <linux/dma/sprd-dma.h>
14 #include "sprd-pcm-dma.h"
31 #define SPRD_COMPR_IRAM_LINKLIST_SIZE (1024 - SPRD_COMPR_IRAM_INFO_SIZE)
36 /* Stage 1 DDR buffer size definition */
52 * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59 * power-on) and DDR buffer. The source channel will transfer data from IRAM
62 * DDR buffer to IRAM buffer.
[all …]
/kernel/linux/linux-5.10/drivers/edac/
DKconfig6 config EDAC_ATOMIC_SCRUB
9 config EDAC_SUPPORT
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
34 config EDAC_DEBUG
40 levels are 0-4 (from low to high) and by default it is set to 2.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config TEGRA_MC
13 config TEGRA20_EMC
19 select DDR
26 config TEGRA30_EMC
31 select DDR
38 config TEGRA124_EMC
50 config TEGRA210_EMC_TABLE
54 config TEGRA210_EMC
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dsuspend-imx53.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
44 /* Save pad config */
60 /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
66 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
72 /* Set pad config */
99 /* Restore pad config */
115 /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
121 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
134 .word . - imx53_suspend
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dsuspend-imx53.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
44 /* Save pad config */
60 /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
66 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
72 /* Set pad config */
99 /* Restore pad config */
115 /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
121 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
134 .word . - imx53_suspend
/kernel/linux/linux-5.10/drivers/mtd/lpddr/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 config MTD_LPDDR
10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
13 config MTD_QINFO_PROBE
22 config MTD_LPDDR2_NVM
25 tristate "Support for LPDDR2-NVM flash chips"
27 This option enables support of PCM memories with a LPDDR2-NVM
/kernel/linux/linux-6.6/drivers/mtd/lpddr/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 config MTD_LPDDR
10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
13 config MTD_QINFO_PROBE
22 config MTD_LPDDR2_NVM
25 tristate "Support for LPDDR2-NVM flash chips"
27 This option enables support of PCM memories with a LPDDR2-NVM
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.
8 supports generic pin config.
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
19 imx7ulp-pinfunc.h in the device tree source folder.
20 The last integer CONFIG is the pad setting value like
21 pull-up on this pin.
24 CONFIG settings.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.
8 supports generic pin config.
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
19 imx7ulp-pinfunc.h in the device tree source folder.
20 The last integer CONFIG is the pad setting value like
21 pull-up on this pin.
24 CONFIG settings.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
[all …]
/kernel/linux/linux-5.10/drivers/devfreq/event/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
17 config DEVFREQ_EVENT_EXYNOS_NOCP
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
26 config DEVFREQ_EVENT_EXYNOS_PPMU
31 This add the devfreq-event driver for Exynos SoC. It provides PPMU
[all …]
/kernel/linux/linux-6.6/drivers/devfreq/event/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
17 config DEVFREQ_EVENT_EXYNOS_NOCP
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
26 config DEVFREQ_EVENT_EXYNOS_PPMU
31 This add the devfreq-event driver for Exynos SoC. It provides PPMU
[all …]
/kernel/linux/linux-6.6/drivers/clk/baikal-t1/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config CLK_BAIKAL_T1
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
17 config CLK_BT1_CCU_PLL
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
30 config CLK_BT1_CCU_DIV
[all …]
/kernel/linux/linux-5.10/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 config ARM_CCI_PMU
17 If compiled as a module, it will be called arm-cci.
19 config ARM_CCI400_PMU
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
28 config ARM_CCI5xx_PMU
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
37 config ARM_CCN
[all …]
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
47 /* DDR Perf hardware feature */
52 unsigned int quirks; /* quirks needed for different DDR Perf core */
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
96 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
118 int cap = (long)ea->var; in ddr_perf_filter_cap_show()
148 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
170 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
[all …]

12345678910>>...17