| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/perf/ |
| D | fsl-imx-ddr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
[all …]
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| D | amlogic,g12-ddr-pmu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic G12 DDR performance monitor
10 - Jiucheng Xu <jiucheng.xu@amlogic.com>
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
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| D | marvell-cn10k-ddr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN10K DDR performance monitor
10 - Bharat Bhushan <bbhushan2@marvell.com>
15 - enum:
16 - marvell,cn10k-ddr-pmu
22 - compatible
23 - reg
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/perf/ |
| D | fsl-imx-ddr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mp-ddr-pmu
[all …]
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| /kernel/linux/linux-6.6/drivers/perf/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
[all …]
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| D | fsl_imx8_ddr_perf.c | 1 // SPDX-License-Identifier: GPL-2.0
43 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
50 /* DDR Perf hardware feature */
55 unsigned int quirks; /* quirks needed for different DDR Perf core */
56 const char *identifier; /* system PMU identifier for userspace */
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
[all …]
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| D | marvell_cn10k_ddr_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0
48 /* Two dedicated event counters for DDR reads and writes */
54 * DO NOT change these event-id numbers, they are used to
125 struct pmu pmu; member
135 #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
144 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in cn10k_ddr_pmu_event_show()
217 PMU_FORMAT_ATTR(event, "config:0-8");
233 struct cn10k_ddr_pmu *pmu = dev_get_drvdata(dev); in cn10k_ddr_perf_cpumask_show() local
235 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in cn10k_ddr_perf_cpumask_show()
274 *event_bitmap = (1ULL << (eventid - 1)); in ddr_perf_get_event_bitmap()
[all …]
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| D | fsl_imx9_ddr_perf.c | 1 // SPDX-License-Identifier: GPL-2.0
32 * 32bit counters monitor counter-specific events in addition to counting reference events
45 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
53 const char *identifier; /* system PMU identifier for userspace */
57 struct pmu pmu; member
75 {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
84 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
86 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
104 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
106 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
[all …]
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| /kernel/linux/linux-6.6/Documentation/admin-guide/perf/ |
| D | alibaba_pmu.rst | 2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
18 The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
19 For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
[all …]
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| D | index.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 hisi-pmu
11 hisi-pcie-pmu
12 hns3-pmu
13 imx-ddr
16 arm-ccn
17 arm-cmn
18 xgene-pmu
20 thunderx2-pmu
22 nvidia-pmu
[all …]
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| D | hisi-pmu.rst | 2 HiSilicon SoC uncore Performance Monitoring Unit (PMU)
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
15 HiSilicon SoC uncore PMU driver
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
39 ID used to count the uncore PMU event.
[all …]
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| D | imx-ddr.rst | 2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
39 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
[all …]
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| D | meson-ddr-pmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
24 Below are DDR access request event filter keywords:
26 + arm - from CPU
27 + vpu_read1 - from OSD + VPP read
28 + gpu - from 3D GPU
29 + pcie - from PCIe controller
30 + hdcp - from HDCP controller
[all …]
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | fsl_imx8_ddr_perf.c | 1 // SPDX-License-Identifier: GPL-2.0
40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
47 /* DDR Perf hardware feature */
52 unsigned int quirks; /* quirks needed for different DDR Perf core */
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
74 struct pmu pmu; member
94 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) in ddr_perf_filter_cap_get() argument
96 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
[all …]
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
[all …]
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/ |
| D | 0010_linux_tools.patch | 7 Change-Id: Iae021412b0487eb94f4a92f5d54464fb539e5ef8
9 diff --git a/Makefile b/Makefile
11 --- a/Makefile
13 @@ -496,7 +496,6 @@ LINUXINCLUDE := \
14 KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE
15 KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs \
16 -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE \
17 - -Werror=implicit-function-declaration -Werror=implicit-int \
18 -Werror=return-type -Wno-format-security \
19 -std=gnu89
[all …]
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| /kernel/linux/linux-5.10/Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
39 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
[all …]
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| D | index.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 hisi-pmu
11 imx-ddr
14 arm-ccn
15 arm-cmn
16 xgene-pmu
18 thunderx2-pmu
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8-ss-ddr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
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| D | imx8dxl-ss-ddr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "fsl,imx8-ddr-pmu";
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
20 Node to get DDR loading. Refer to
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
[all …]
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| /kernel/linux/linux-6.6/drivers/perf/hisilicon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "HiSilicon SoC PMU drivers"
7 Agent performance monitor and DDR Controller performance monitor.
10 tristate "HiSilicon PCIE PERF PMU"
13 Provide support for HiSilicon PCIe performance monitoring unit (PMU)
15 Adds the PCIe PMU into perf events system for monitoring latency,
19 tristate "HNS3 PERF PMU"
23 Provide support for HNS3 performance monitoring unit (PMU) RCiEP
25 Adds the HNS3 PMU into perf events system for monitoring latency,
|
| /kernel/linux/linux-6.6/drivers/perf/amlogic/ |
| D | meson_g12_ddr_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0
43 PMU_FORMAT_ATTR(event, "config:0-7");
127 /* calculate ddr clock */
135 val = readl(info->pll_reg); in dmc_g12_get_freq_quick()
179 r = readl(db->ddr_reg[0] + (DMC_MON_G12_CTRL0 + (i << 2))); in g12_dump_reg()
182 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT); in g12_dump_reg()
184 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT); in g12_dump_reg()
186 r = readl(db->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT); in g12_dump_reg()
188 r = readl(db->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT); in g12_dump_reg()
190 r = readl(db->ddr_reg[0] + DMC_MON_G12_THD_GRANT_CNT); in g12_dump_reg()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
19 It should be a DCF interrupt. When DDR DVFS finishes
[all …]
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| /kernel/linux/linux-5.10/drivers/perf/hisilicon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "HiSilicon SoC PMU drivers"
7 Agent performance monitor and DDR Controller performance monitor.
|