Searched full:ddr52 (Results 1 – 25 of 36) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 99 ti,otap-del-sel-ddr52:
100 description: Output tap delay for eMMC DDR52 timing
151 ti,itap-del-sel-ddr52:
152 description: Input tap delay for MMC DDR52 timing
211 ti,otap-del-sel-ddr52 = <0x5>;
216 ti,itap-del-sel-ddr52 = <0x3>;
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| D | sdhci-sprd.txt | 38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
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| D | mmc-controller.yaml | 339 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 109 ti,otap-del-sel-ddr52:
110 description: Output tap delay for eMMC DDR52 timing
167 ti,itap-del-sel-ddr52:
168 description: Input tap delay for MMC DDR52 timing
234 ti,otap-del-sel-ddr52 = <0x5>;
239 ti,itap-del-sel-ddr52 = <0x3>;
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| D | sdhci-sprd.txt | 38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
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| D | mmc-controller.yaml | 348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | dw_mmc-k3.c | 85 {0}, /* 8: DDR52 */
97 {0}, /* 8: DDR52 */
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| D | sdhci_am654.c | 130 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
131 "ti,itap-del-sel-ddr52",
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| D | dw_mmc-rockchip.c | 44 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
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| D | sdhci-sprd.c | 96 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
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| D | sdhci-acpi.c | 573 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | dw_mmc-k3.c | 85 {0}, /* 8: DDR52 */
97 {0}, /* 8: DDR52 */
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| D | sdhci-acpi.c | 499 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
500 * happens while in DDR52 and HS modes. This has not been observed to in amd_select_drive_strength()
532 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
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| D | sdhci_am654.c | 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
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| D | dw_mmc-rockchip.c | 46 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
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| D | sdhci-sprd.c | 111 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
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| /kernel/linux/linux-5.10/drivers/mmc/core/ |
| D | debugfs.c | 144 str = "mmc DDR52"; in mmc_ios_show()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 148 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 150 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
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| /kernel/linux/linux-6.6/drivers/mmc/core/ |
| D | debugfs.c | 145 str = "mmc DDR52"; in mmc_ios_show()
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| D | host.c | 257 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-ddr52", in mmc_of_parse_clk_phase()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am65-main.dtsi | 279 ti,otap-del-sel-ddr52 = <0x5>;
301 ti,otap-del-sel-ddr52 = <0x4>;
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| D | k3-j7200-main.dtsi | 397 ti,otap-del-sel-ddr52 = <0x6>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/ |
| D | k3-am64-main.dtsi | 613 ti,otap-del-sel-ddr52 = <0x6>;
617 ti,itap-del-sel-ddr52 = <0x3>;
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| D | k3-am65-main.dtsi | 447 ti,otap-del-sel-ddr52 = <0x5>;
469 ti,otap-del-sel-ddr52 = <0x4>;
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