Home
last modified time | relevance | path

Searched +full:edp +full:- +full:phy (Results 1 – 25 of 158) sorted by relevance

1234567

/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include <dt-bindings/phy/phy.h>
24 #include "phy-qcom-qmp.h"
74 /* DP PHY swing and pre_emphasis tables */
85 struct phy *phy; member
87 void __iomem *edp; member
173 static int qcom_edp_phy_init(struct phy *phy) in qcom_edp_phy_init() argument
175 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_init() local
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm eDP PHY
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
20 - qcom,sc7280-edp-phy
21 - qcom,sc8180x-edp-phy
22 - qcom,sc8280xp-dp-phy
[all …]
Drockchip,rk3288-dp-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
22 "#phy-cells":
26 - compatible
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/
Dedp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
33 /* the encoder we are hooked to (outside of eDP block) */
41 /* eDP bridge */
42 struct drm_bridge *msm_edp_bridge_init(struct msm_edp *edp);
45 /* eDP connector */
46 struct drm_connector *msm_edp_connector_init(struct msm_edp *edp);
55 /* Phy */
56 bool msm_edp_phy_ready(struct edp_phy *phy);
57 void msm_edp_phy_ctrl(struct edp_phy *phy, int enable);
[all …]
Dedp_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include "edp.h"
7 #include "edp.xml.h"
15 bool msm_edp_phy_ready(struct edp_phy *phy) in msm_edp_phy_ready() argument
20 while (--cnt) { in msm_edp_phy_ready()
21 status = edp_read(phy->base + in msm_edp_phy_ready()
29 pr_err("%s: PHY NOT ready\n", __func__); in msm_edp_phy_ready()
36 void msm_edp_phy_ctrl(struct edp_phy *phy, int enable) in msm_edp_phy_ctrl() argument
41 edp_write(phy->base + REG_EDP_PHY_CTRL, in msm_edp_phy_ctrl()
[all …]
Dedp_ctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
13 #include "edp.h"
14 #include "edp.xml.h"
25 #define EDP_TRAIN_FAIL -1
109 struct edp_phy *phy; member
144 struct platform_device *pdev = ctrl->pdev; in edp_clk_init()
147 ctrl->aux_clk = msm_clk_get(pdev, "core"); in edp_clk_init()
148 if (IS_ERR(ctrl->aux_clk)) { in edp_clk_init()
149 ret = PTR_ERR(ctrl->aux_clk); in edp_clk_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
28 edp/edp.o \
29 edp/edp_aux.o \
30 edp/edp_bridge.o \
31 edp/edp_connector.o \
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
[all …]
Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
[all …]
Dqcom,sc7280-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
16 See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
20 const: qcom,sc7280-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Danalogix_dp.txt3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
16 -clock-names:
18 -phys:
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsc8280xp-crd.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sc8280xp-pmics.dtsi"
17 compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
26 compatible = "pwm-backlight";
28 enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
29 power-supply = <&vreg_edp_bl>;
31 pinctrl-names = "default";
[all …]
Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
[all …]
Dsc8280xp-lenovo-thinkpad-x13s.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/
Danalogix_dp-rockchip.txt5 - compatible: "rockchip,rk3288-dp",
6 "rockchip,rk3399-edp";
8 - reg: physical base address of the controller and length
10 - clocks: from common clock binding: handle to dp clock.
13 - clock-names: from common clock binding:
16 - resets: Must contain an entry for each entry in reset-names.
19 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20 - pinctrl-0: pin-control mode. should be <&edp_hpd>
22 - reset-names: Must include the name "dp"
24 - rockchip,grf: this soc should set GRF regs, so need get grf here.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Drockchip-dp-phy.txt1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
21 compatible = "rockchip,rk3288-dp-phy";
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/
Dlink_service_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
47 /* eDP version 1.1 or lower */
49 /* eDP version 1.2 */
51 /* eDP version 1.3 */
97 /* phy test patterns*/
139 /* standard mode for eDP */
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_ddi.c54 u32 trans1; /* balance leg enable, de-emph level */
246 * eDP 1.4 low vswing translation parameters
263 * eDP 1.4 low vswing translation parameters
280 * eDP 1.4 low vswing translation parameters
360 /* BSpec has 2 recommended values - entries 0 and 8.
412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
592 /* Voltage swing pre-emphasis */
606 /* Voltage swing pre-emphasis */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Dmdp5.txt6 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
11 - compatible:
12 * "qcom,mdss" - MDSS
13 - reg: Physical base address and length of the controller's registers.
14 - reg-names: The names of register regions. The following regions are required:
17 - interrupts: The interrupt signal from MDSS.
18 - interrupt-controller: identifies the node as an interrupt controller.
19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
21 - power-domains: a power domain consumer specifier according to
23 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_dp.c107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
132 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
133 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
146 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ in intel_dp_set_dpcd_sink_rates()
149 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates()
150 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); in intel_dp_set_dpcd_sink_rates()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.txt5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
17 - phy-names: must contain "dphy"
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/
Dlink_service_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 /* eDP version 1.1 or lower */
45 /* eDP version 1.2 */
47 /* eDP version 1.3 */
76 /* TODO - factor lane_settings out because it changes during LT */
100 * training states - parameters that can change in link training
106 * a constant input pre-decided prior to link training.
124 /* phy test patterns*/
182 /* standard mode for eDP */

1234567