Home
last modified time | relevance | path

Searched +full:enable +full:- +full:frequency +full:- +full:shift (Results 1 – 25 of 824) sorted by relevance

12345678910>>...33

/kernel/linux/linux-6.6/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
[all …]
/kernel/linux/linux-6.6/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
65 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
67 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
74 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
76 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
85 * Fv is derived from the variable frequency output. The variable frequency
88 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
90 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
[all …]
/kernel/linux/linux-6.6/include/linux/
Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
35 * struct clocksource - hardware abstraction for a free running counter
36 * Provides mostly state-free accessors to the underlying hardware.
43 * @shift: Cycle to nanosecond divisor (power of two)
48 * @archdata: Optional arch-specific data
57 * 1-99: Unfit for real use
59 * 100-199: Base level usability.
61 * 200-299: Good.
63 * 300-399: Desired.
65 * 400-499: Perfect
[all …]
/kernel/linux/linux-5.10/include/linux/
Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct clocksource - hardware abstraction for a free running counter
35 * Provides mostly state-free accessors to the underlying hardware.
42 * @shift: Cycle to nanosecond divisor (power of two)
47 * @archdata: Optional arch-specific data
56 * 1-99: Unfit for real use
58 * 100-199: Base level usability.
60 * 200-299: Good.
62 * 300-399: Desired.
64 * 400-499: Perfect
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/
Dapll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
24 "autoidle" - contains the autoidle register offset (OMAP2 only)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Dapll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
24 "autoidle" - contains the autoidle register offset (OMAP2 only)
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
64 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
66 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
73 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
75 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
84 * Fv is derived from the variable frequency output. The variable frequency
87 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
89 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/
Dmax8973-regulator.txt5 - compatible: must be one of following:
8 - reg: the i2c slave address of the regulator. It should be 0x1b.
15 -maxim,externally-enable: boolean, externally control the regulator output
16 enable/disable.
17 -maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided
18 then externally enable control will be considered.
19 -maxim,dvs-gpio: GPIO which is connected to DVS pin of device.
20 -maxim,dvs-default-state: Default state of GPIO during initialisation.
22 -maxim,enable-remote-sense: boolean, enable reote sense.
23 -maxim,enable-falling-slew-rate: boolean, enable falling slew rate.
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
16 * clock frequency of the oscillator in combination with the TIMINCA
21 * of only a right shift (division by power of 2). The following math
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
40 * The calculated value allows us to right shift the SYSTIME register
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbe/
Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
16 * clock frequency of the oscillator in combination with the TIMINCA
21 * of only a right shift (division by power of 2). The following math
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
40 * The calculated value allows us to right shift the SYSTIME register
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
54 * *--------------+ +--------------+
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu_mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
22 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
23 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
24 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
27 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
28 return common->prediv; in ccu_mux_get_prediv()
30 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
32 parent_index = reg >> cm->shift; in ccu_mux_get_prediv()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/clk/bcm/
Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
27 /* number of VCO frequency bands */
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
103 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
[all …]
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-iproc-pll.c16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
37 /* number of VCO frequency bands */
100 return -EINVAL; in pll_calc_param()
102 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
112 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
113 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
114 vco_out->pdiv = 1; in pll_calc_param()
[all …]
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
Dccu_mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
24 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
25 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
26 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
29 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
30 return common->prediv; in ccu_mux_get_prediv()
32 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
34 parent_index = reg >> cm->shift; in ccu_mux_get_prediv()
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
68 __kernel_long_t freq; /* frequency offset (scaled ppm) */
74 __kernel_long_t tolerance;/* clock frequency tolerance (ppm)
80 __kernel_long_t ppsfreq;/* pps frequency (scaled ppm) (ro) */
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
68 __kernel_long_t freq; /* frequency offset (scaled ppm) */
74 __kernel_long_t tolerance;/* clock frequency tolerance (ppm)
80 __kernel_long_t ppsfreq;/* pps frequency (scaled ppm) (ro) */
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/realtek/
Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/realtek/
Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/
Dmaxim,max8973.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
18 - maxim,max8973
19 - maxim,max77621
21 junction-warn-millicelsius:
30 maxim,dvs-gpio:
35 maxim,dvs-default-state:
[all …]
/kernel/linux/linux-5.10/arch/powerpc/kernel/
Dtime.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Converted for 64-bit by Mike Corrigan (mikejc@us.ibm.com)
11 * to make clock more stable (2.4.0-test5). The only thing
20 * - improve precision and reproducibility of timebase frequency
22 * - for astronomical applications: add a new function to get
26 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
49 #include <linux/posix-timers.h>
72 #include <asm/asm-prototypes.h>
146 * microseconds. This is stored as 0.64 fixed-point binary fraction.
186 u64 i = local_paca->dtl_ridx; in scan_dispatch_log()
[all …]

12345678910>>...33