| /kernel/linux/linux-6.6/arch/mips/bcm63xx/ |
| D | clk.c | 23 unsigned int rate; member
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
56 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
79 * Ethernet MAC clocks: only relevant on 6358, silently enable misc
80 * clocks
92 if (clk->id == 0) in enetx_set()
355 .rate = (50 * 1000 * 1000),
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| /kernel/linux/linux-5.10/arch/mips/bcm63xx/ |
| D | clk.c | 23 unsigned int rate; member
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
56 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
79 * Ethernet MAC clocks: only revelant on 6358, silently enable misc
80 * clocks
92 if (clk->id == 0) in enetx_set()
355 .rate = (50 * 1000 * 1000),
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/reset-controller.h>
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
27 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) in qcom_find_freq() argument
32 if (!f->freq) in qcom_find_freq()
35 for (; f->freq; f++) in qcom_find_freq()
36 if (rate <= f->freq) in qcom_find_freq()
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/reset-controller.h>
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
27 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) in qcom_find_freq() argument
32 if (!f->freq) in qcom_find_freq()
35 for (; f->freq; f++) in qcom_find_freq()
36 if (rate <= f->freq) in qcom_find_freq()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
20 * @lock: maintains exclusion between callbacks for a given clock-provider.
21 * @clk_data: holds clock related data like clk_hw* and number of clocks.
53 * struct samsung_fixed_rate_clock: information about fixed-rate clock
55 * @name: name of this fixed-rate clock.
57 * @flags: optional fixed-rate clock flags.
58 * @fixed-rate: fixed clock rate of this clock.
78 * struct samsung_fixed_factor_clock: information about fixed-factor clock
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/ |
| D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
16 - clocks: parent clock.
19 - clock-output-names : from common clock binding.
20 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
16 - clocks: parent clock.
19 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
21 - reg: offset for the autoidle register of this clock, see [2]
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
19 * @lock: maintains exclusion between callbacks for a given clock-provider.
20 * @clk_data: holds clock related data like clk_hw* and number of clocks.
52 * struct samsung_fixed_rate_clock: information about fixed-rate clock
54 * @name: name of this fixed-rate clock.
56 * @flags: optional fixed-rate clock flags.
57 * @fixed-rate: fixed clock rate of this clock.
77 * struct samsung_fixed_factor_clock: information about fixed-factor clock
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-car.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 for muxing and gating Tegra's clocks, and setting their rates.
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
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| D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - allwinner,sun4i-a10-pll3-2x-clk
17 - fixed-factor-clock
19 "#clock-cells":
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|
| D | samsung,s5pv210-clock.txt | 9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
20 All available clocks are defined as preprocessor macros in
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
27 clock-output-names:
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|
| D | clk-s5pv210-audss.txt | 3 The Samsung Audio Subsystem clock controller generates and supplies clocks
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
16 not specified (i.e. xusbxti is used for PLL reference), it is fixed to
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
19 - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
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|
| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
10 value of a #clock-cells property in the clock provider node.
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
22 clock-output-names: Recommended to be a list of strings of clock output signal
24 However, the meaning of clock-output-names is domain
33 the provider's clock-output-names property.
38 #clock-cells = <1>;
39 clock-output-names = "ckil", "ckih";
42 - this node defines a device with two clock outputs, the first named
44 clocks by index. The names should reflect the clock output signal
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|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - fixed-factor-clock
18 "#clock-cells":
21 clocks:
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| D | samsung,s5pv210-audss-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 All available clocks are defined as preprocessor macros in
17 include/dt-bindings/clock/s5pv210-audss.h header.
[all …]
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| D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
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|
| D | canaan,k210-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
24 clocks:
27 Phandle of the SoC 26MHz fixed-rate oscillator clock.
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
76 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
86 multi-function device has one fixed-rate oscillator, clocked
93 This driver provides support for clocks that are controlled
103 This driver provides support for clocks that are controlled
117 be pre-programmed to support other configurations and features not yet
159 This driver supports the clocks on Bitmain BM1880 SoC.
166 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
176 For example, the CDCE925 contains two PLLs with spread-spectrum
178 the following setup, and uses a fixed setting for the output muxes.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra20-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
34 clocks:
40 dma-names:
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| D | nvidia,tegra20-spdif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
35 clocks:
38 clock-names:
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| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
68 generators of audio clocks.
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
105 This driver provides support for clocks that are controlled
115 This driver provides support for clocks that are controlled
129 be pre-programmed to support other configurations and features not yet
171 This driver supports the clocks on Bitmain BM1880 SoC.
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
[all …]
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| /kernel/linux/linux-6.6/Documentation/sound/soc/ |
| D | clocking.rst | 10 ------------
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
22 DAI Clocks
23 ----------
30 runs at exactly the sample rate (LRC = Rate).
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
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| /kernel/linux/linux-5.10/Documentation/sound/soc/ |
| D | clocking.rst | 10 ------------
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
22 DAI Clocks
23 ----------
30 runs at exactly the sample rate (LRC = Rate).
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imgtec/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 Enable this to support the system & CPU clocks on the MIPS Boston
9 fixed rate clocks whose rate is determined by reading a platform
|