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/kernel/linux/linux-5.10/arch/arm/mach-tegra/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
48 * the flow controller state is cleared (which will cause the in tegra20_boot_secondary()
49 * flow controller to stop driving reset if the CPU has been in tegra20_boot_secondary()
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
57 * Unhalt the CPU. If the flow controller was used to in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
65 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-tegra/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
48 * the flow controller state is cleared (which will cause the in tegra20_boot_secondary()
49 * flow controller to stop driving reset if the CPU has been in tegra20_boot_secondary()
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
57 * Unhalt the CPU. If the flow controller was used to in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
65 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
[all …]
/kernel/linux/linux-6.6/Documentation/hwmon/
Daquacomputer_d5next.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver aquacomputer-d5next
10 * Aquacomputer Farbwerk RGB controller
11 * Aquacomputer Farbwerk 360 RGB controller
12 * Aquacomputer Octo fan controller
13 * Aquacomputer Quadro fan controller
14 * Aquacomputer High Flow Next sensor
18 * Aquacomputer Poweradjust 3 fan controller
23 -----------
29 virtual temperature sensors, as well as two flow sensors. The fans expose their
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/kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/intel/
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for the Intel(R) Ethernet Controller 700 Series
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
34 * Intel(R) Ethernet Controller X710
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Dfm10k.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for Intel(R) Ethernet Multi-host Controller
8 Copyright(c) 2015-2018 Intel Corporation.
12 - Identifying Your Adapter
13 - Additional Configurations
14 - Performance Tuning
15 - Known Issues
16 - Support
21 Ethernet Multi-host Controller.
28 Flow Control
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Dixgbe.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Known Issues
17 - Support
23 * Intel(R) Ethernet Controller 82598
24 * Intel(R) Ethernet Controller 82599
25 * Intel(R) Ethernet Controller X520
[all …]
/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/intel/
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for the Intel(R) Ethernet Controller 700 Series
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
34 * Intel(R) Ethernet Controller X710
[all …]
Dfm10k.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for Intel(R) Ethernet Multi-host Controller
8 Copyright(c) 2015-2018 Intel Corporation.
12 - Identifying Your Adapter
13 - Additional Configurations
14 - Performance Tuning
15 - Known Issues
16 - Support
21 Ethernet Multi-host Controller.
28 Flow Control
[all …]
Dixgbe.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Known Issues
17 - Support
23 * Intel(R) Ethernet Controller 82598
24 * Intel(R) Ethernet Controller 82599
25 * Intel(R) Ethernet Controller X520
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/nfc/
Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell International Ltd. NCI NFC controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dcirrus,clps711x-intc.txt1 Cirrus Logic CLPS711X Interrupt Controller
5 - compatible: Should be "cirrus,ep7209-intc".
6 - reg: Specifies base physical address of the registers set.
7 - interrupt-controller: Identifies the node as an interrupt controller.
8 - #interrupt-cells: Specifies the number of cells needed to encode an
13 ---------------------------
20 8: TC1OI TC1 under flow
21 9: TC2OI TC2 under flow
36 intc: interrupt-controller {
37 compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dcirrus,clps711x-intc.txt1 Cirrus Logic CLPS711X Interrupt Controller
5 - compatible: Should be "cirrus,ep7209-intc".
6 - reg: Specifies base physical address of the registers set.
7 - interrupt-controller: Identifies the node as an interrupt controller.
8 - #interrupt-cells: Specifies the number of cells needed to encode an
13 ---------------------------
20 8: TC1OI TC1 under flow
21 9: TC2OI TC2 under flow
36 intc: interrupt-controller {
37 compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
[all …]
/kernel/linux/linux-6.6/Documentation/gpu/
Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
39 -------------------
47 --------------------------
52 -----------------------------
56 Timing controller (timing_ctrlr)
57 --------------------------------
58 Final stage of display pipeline, Timing controller is not for the pixel
62 ------
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/kernel/linux/linux-5.10/Documentation/gpu/
Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
23 -----
30 ------
39 -------------------
47 --------------------------
52 -----------------------------
56 Timing controller (timing_ctrlr)
57 --------------------------------
58 Final stage of display pipeline, Timing controller is not for the pixel
62 ------
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/kernel/linux/linux-6.6/arch/mips/mti-malta/
Dmalta-init.c21 #include <asm/smp-ops.h>
24 #include <asm/mips-cps.h>
25 #include <asm/mips-boards/generic.h>
26 #include <asm/mips-boards/malta.h>
31 /* Bonito64 system controller register base. */
35 /* GT64120 system controller register base */
38 /* MIPS System controller register base */
46 char parity = '\0', bits = '\0', flow = '\0'; in console_config() local
52 baud = baud*10 + *s++ - '0'; in console_config()
64 flow = 'r'; in console_config()
[all …]
/kernel/linux/linux-5.10/arch/mips/mti-malta/
Dmalta-init.c21 #include <asm/smp-ops.h>
24 #include <asm/mips-cps.h>
25 #include <asm/mips-boards/generic.h>
26 #include <asm/mips-boards/malta.h>
31 /* Bonito64 system controller register base. */
35 /* GT64120 system controller register base */
38 /* MIPS System controller register base */
46 char parity = '\0', bits = '\0', flow = '\0'; in console_config() local
52 baud = baud*10 + *s++ - '0'; in console_config()
64 flow = 'r'; in console_config()
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/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
147 /* GMAC FLOW CTRL defines */
151 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
152 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
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/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
147 /* GMAC FLOW CTRL defines */
151 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
152 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-flowctrl.txt1 NVIDIA Tegra Flow Controller
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra20-flowctrl": for Tegra20
6 - "nvidia,tegra30-flowctrl": for Tegra30
7 - "nvidia,tegra114-flowctrl": for Tegra114
8 - "nvidia,tegra124-flowctrl": for Tegra124
9 - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
10 - "nvidia,tegra210-flowctrl": for Tegra210
11 - reg: Should contain one register range (address and length)
15 flow-controller@60007000 {
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dqcom_adm.txt1 QCOM ADM DMA Controller
4 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
5 - reg: Address range for DMA registers
6 - interrupts: Should contain one interrupt shared by all channels
7 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
8 denotes CRCI (client rate control interface) flow control assignment.
9 - clocks: Should contain the core clock and interface clock.
10 - clock-names: Must contain "core" for the core clock and "iface" for the
12 - resets: Must contain an entry for each entry in reset names.
13 - reset-names: Must include the following entries:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-flowctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-flowctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Flow Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-flowctrl
18 - nvidia,tegra30-flowctrl
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dmilbeaut-uart.txt1 Socionext Milbeaut UART controller
4 - compatible: should be "socionext,milbeaut-usio-uart".
5 - reg: offset and length of the register set for the device.
6 - interrupts: two interrupts specifier.
7 - interrupt-names: should be "rx", "tx".
8 - clocks: phandle to the input clock.
11 - auto-flow-control: flow control enable.
15 compatible = "socionext,milbeaut-usio-uart";
18 interrupt-names = "rx", "tx";
20 auto-flow-control;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dmilbeaut-uart.txt1 Socionext Milbeaut UART controller
4 - compatible: should be "socionext,milbeaut-usio-uart".
5 - reg: offset and length of the register set for the device.
6 - interrupts: two interrupts specifier.
7 - interrupt-names: should be "rx", "tx".
8 - clocks: phandle to the input clock.
11 - auto-flow-control: flow control enable.
15 compatible = "socionext,milbeaut-usio-uart";
18 interrupt-names = "rx", "tx";
20 auto-flow-control;
/kernel/linux/linux-6.6/Documentation/core-api/
Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
15 handle all the different types of interrupt controller hardware. Device
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
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/kernel/linux/linux-5.10/Documentation/core-api/
Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
15 handle all the different types of interrupt controller hardware. Device
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
[all …]

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