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/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ipq806x.c2 * Qualcomm Atheros IPQ806x GMAC glue layer
93 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_sgmii() argument
95 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
119 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_rgmii() argument
121 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
145 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) in ipq806x_gmac_set_speed() argument
150 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
152 div = get_clk_div_rgmii(gmac, speed); in ipq806x_gmac_set_speed()
153 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
154 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
[all …]
Ddwmac-sunxi.c32 struct sunxi_priv_data *gmac = priv; in sun7i_gmac_init() local
35 if (gmac->regulator) { in sun7i_gmac_init()
36 ret = regulator_enable(gmac->regulator); in sun7i_gmac_init()
41 /* Set GMAC interface port mode in sun7i_gmac_init()
43 * The GMAC TX clock lines are configured by setting the clock in sun7i_gmac_init()
47 if (phy_interface_mode_is_rgmii(gmac->interface)) { in sun7i_gmac_init()
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
50 gmac->clk_enabled = 1; in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
[all …]
Ddwmac-anarion.c27 static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) in gmac_read_reg() argument
29 return readl((void *)(gmac->ctl_block + reg)); in gmac_read_reg()
32 static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) in gmac_write_reg() argument
34 writel(val, (void *)(gmac->ctl_block + reg)); in gmac_write_reg()
40 struct anarion_gmac *gmac = priv; in anarion_gmac_init() local
43 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 1); in anarion_gmac_init()
45 sw_config = gmac_read_reg(gmac, GMAC_SW_CONFIG_REG); in anarion_gmac_init()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
48 gmac_write_reg(gmac, GMAC_SW_CONFIG_REG, sw_config); in anarion_gmac_init()
50 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 0); in anarion_gmac_init()
[all …]
Ddwmac-sun8i.c36 * @syscon_field reg_field for the syscon's gmac register
549 struct sunxi_priv_data *gmac = priv; in sun8i_dwmac_init() local
552 if (gmac->regulator) { in sun8i_dwmac_init()
553 ret = regulator_enable(gmac->regulator); in sun8i_dwmac_init()
560 ret = clk_prepare_enable(gmac->tx_clk); in sun8i_dwmac_init()
566 if (gmac->use_internal_phy) { in sun8i_dwmac_init()
575 clk_disable_unprepare(gmac->tx_clk); in sun8i_dwmac_init()
577 if (gmac->regulator) in sun8i_dwmac_init()
578 regulator_disable(gmac->regulator); in sun8i_dwmac_init()
745 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in get_ephy_nodes() local
[all …]
DKconfig61 tristate "Adaptrum Anarion GMAC support"
65 Support for Adaptrum Anarion GMAC Ethernet controller.
91 tristate "MediaTek MT27xx GMAC support"
94 Support for MediaTek GMAC Ethernet controller.
154 tristate "STi GMAC support"
163 SOCs GMAC ethernet controller.
175 SOCs GMAC ethernet controller.
178 tristate "Allwinner GMAC support"
182 Support for Allwinner A20/A31 GMAC ethernet controllers.
186 GMAC ethernet controller.
[all …]
Dhwif.c60 /* GMAC older than 3.50 has no extended descriptors */ in stmmac_dwmac1_quirks()
91 bool gmac; member
109 .gmac = false,
127 .gmac = true,
145 .gmac = false,
163 .gmac = false,
181 .gmac = false,
199 .gmac = false,
217 .gmac = false,
236 .gmac = false,
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ipq806x.c2 * Qualcomm Atheros IPQ806x GMAC glue layer
115 static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_sgmii() argument
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
141 static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) in get_clk_div_rgmii() argument
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
167 static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) in ipq806x_gmac_set_speed() argument
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
174 div = get_clk_div_rgmii(gmac, speed); in ipq806x_gmac_set_speed()
175 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
176 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
[all …]
Ddwmac-sunxi.c32 struct sunxi_priv_data *gmac = priv; in sun7i_gmac_init() local
35 if (gmac->regulator) { in sun7i_gmac_init()
36 ret = regulator_enable(gmac->regulator); in sun7i_gmac_init()
41 /* Set GMAC interface port mode in sun7i_gmac_init()
43 * The GMAC TX clock lines are configured by setting the clock in sun7i_gmac_init()
47 if (phy_interface_mode_is_rgmii(gmac->interface)) { in sun7i_gmac_init()
48 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); in sun7i_gmac_init()
49 clk_prepare_enable(gmac->tx_clk); in sun7i_gmac_init()
50 gmac->clk_enabled = 1; in sun7i_gmac_init()
52 clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); in sun7i_gmac_init()
[all …]
Ddwmac-anarion.c27 static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) in gmac_read_reg() argument
29 return readl(gmac->ctl_block + reg); in gmac_read_reg()
32 static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) in gmac_write_reg() argument
34 writel(val, gmac->ctl_block + reg); in gmac_write_reg()
40 struct anarion_gmac *gmac = priv; in anarion_gmac_init() local
43 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 1); in anarion_gmac_init()
45 sw_config = gmac_read_reg(gmac, GMAC_SW_CONFIG_REG); in anarion_gmac_init()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
48 gmac_write_reg(gmac, GMAC_SW_CONFIG_REG, sw_config); in anarion_gmac_init()
50 gmac_write_reg(gmac, GMAC_RESET_CONTROL_REG, 0); in anarion_gmac_init()
[all …]
Ddwmac-sun8i.c38 * @syscon_field reg_field for the syscon's gmac register
588 struct sunxi_priv_data *gmac = priv; in sun8i_dwmac_init() local
591 if (gmac->regulator) { in sun8i_dwmac_init()
592 ret = regulator_enable(gmac->regulator); in sun8i_dwmac_init()
599 if (gmac->use_internal_phy) { in sun8i_dwmac_init()
608 if (gmac->regulator) in sun8i_dwmac_init()
609 regulator_disable(gmac->regulator); in sun8i_dwmac_init()
776 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in get_ephy_nodes() local
797 gmac->ephy_clk = of_clk_get(iphynode, 0); in get_ephy_nodes()
798 if (IS_ERR(gmac->ephy_clk)) in get_ephy_nodes()
[all …]
DKconfig61 tristate "Adaptrum Anarion GMAC support"
65 Support for Adaptrum Anarion GMAC Ethernet controller.
106 tristate "MediaTek MT27xx GMAC support"
109 Support for MediaTek GMAC Ethernet controller.
173 tristate "STi GMAC support"
182 SOCs GMAC ethernet controller.
194 SOCs GMAC ethernet controller.
197 tristate "Allwinner GMAC support"
201 Support for Allwinner A20/A31 GMAC ethernet controllers.
205 GMAC ethernet controller.
[all …]
Dhwif.c60 /* GMAC older than 3.50 has no extended descriptors */ in stmmac_dwmac1_quirks()
104 bool gmac; member
122 .gmac = false,
140 .gmac = true,
158 .gmac = false,
176 .gmac = false,
194 .gmac = false,
212 .gmac = false,
230 .gmac = false,
249 .gmac = false,
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Drockchip-dwmac.yaml7 title: Rockchip 10/100/1000 Ethernet driver(GMAC)
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
23 - rockchip,rk3328-gmac
24 - rockchip,rk3366-gmac
25 - rockchip,rk3368-gmac
26 - rockchip,rk3399-gmac
[all …]
Dhisilicon-hix5hd2-gmac.txt1 Hisilicon hix5hd2 gmac controller
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
Dallwinner,sun7i-a20-gmac.yaml4 $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
7 title: Allwinner A20 GMAC
18 const: allwinner,sun7i-a20-gmac
31 - description: GMAC main clock
56 gmac: ethernet@1c50000 {
57 compatible = "allwinner,sun7i-a20-gmac";
Dsnps,dwmac.yaml38 - st,spear600-gmac
51 - allwinner,sun7i-a20-gmac
54 - allwinner,sun8i-r40-gmac
73 - renesas,r9a06g032-gmac
74 - renesas,rzn1-gmac
75 - rockchip,px30-gmac
76 - rockchip,rk3128-gmac
77 - rockchip,rk3228-gmac
78 - rockchip,rk3288-gmac
79 - rockchip,rk3328-gmac
[all …]
Dmediatek-dwmac.yaml21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
35 - mediatek,mt2712-gmac
39 - mediatek,mt8195-gmac
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
155 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt1 Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
[all …]
Dhisilicon-hix5hd2-gmac.txt1 Hisilicon hix5hd2 gmac controller
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
Dallwinner,sun7i-a20-gmac.yaml4 $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
7 title: Allwinner A20 GMAC Device Tree Bindings
18 const: allwinner,sun7i-a20-gmac
31 - description: GMAC main clock
56 gmac: ethernet@1c50000 {
57 compatible = "allwinner,sun7i-a20-gmac";
/kernel/linux/linux-6.6/drivers/clk/sunxi/
Dclk-a20-gmac.c19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
32 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
36 * Only the GMAC should use this clock. Altering the clock so that it doesn't
37 * match the GMAC's operation parameters will result in the GMAC not being
38 * able to send traffic out. The GMAC driver should set the clock rate and
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-a20-gmac.c19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
32 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
36 * Only the GMAC should use this clock. Altering the clock so that it doesn't
37 * match the GMAC's operation parameters will result in the GMAC not being
38 * able to send traffic out. The GMAC driver should set the clock rate and
[all …]
/kernel/linux/linux-5.10/arch/mips/netlogic/xlr/
Dfmn-config.c91 total_credits += cfg->gmac[0].credit_config[bkt]; in check_credit_distribution()
92 total_credits += cfg->gmac[1].credit_config[bkt]; in check_credit_distribution()
183 struct xlr_fmn_info *gmac = xlr_board_fmn_config.gmac; in xlr_board_info_setup() local
197 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, in xlr_board_info_setup()
207 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, in xlr_board_info_setup()
222 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, in xlr_board_info_setup()
224 setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0, in xlr_board_info_setup()
235 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, in xlr_board_info_setup()
237 setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0, in xlr_board_info_setup()
249 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, in xlr_board_info_setup()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/
Dmt7530.txt45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
47 Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
53 GMAC of the SOC.
55 GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
67 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
69 a ethernet port. But can't interface to the 2nd GMAC.
73 Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
139 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
205 /* Commented out. Port 4 is handled by 2nd GMAC.
/kernel/linux/linux-6.6/drivers/net/ethernet/cortina/
Dgemini.h2 /* Register definitions for Gemini GMAC Ethernet device driver
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
91 /* GMAC 0/1 DMA/TOE register */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
148 /* TOE GMAC 0/1 register */
332 /* GMAC DMA Control Register
366 /* GMAC Tx Weighting Control Register 0
386 /* GMAC Tx Weighting Control Register 1
410 /* GMAC DMA Tx Description Word 0 Register
434 /* GMAC DMA Tx Description Word 1 Register
[all …]

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