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Searched +full:imx8 +full:- +full:ddr +full:- +full:pmu (Results 1 – 12 of 12) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mp-ddr-pmu
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
Dimx8dxl-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "fsl,imx8-ddr-pmu";
Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
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Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
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/kernel/linux/linux-6.6/drivers/perf/
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
43 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
50 /* DDR Perf hardware feature */
55 unsigned int quirks; /* quirks needed for different DDR Perf core */
56 const char *identifier; /* system PMU identifier for userspace */
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0031_linux_drivers_perf_phy_pinctrl_ptp_pwm.patch7 Change-Id: I50a0069a60f92f57dd6112f6a9700811be19e564
9 diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
11 --- a/drivers/perf/fsl_imx8_ddr_perf.c
13 @@ -5,6 +5,7 @@
21 @@ -14,12 +15,15 @@
37 @@ -28,9 +32,18 @@
56 @@ -40,32 +53,56 @@
57 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
66 /* DDR Perf hardware feature */
72 +#define DDR_PERF_TYPE 0x1 /* ddr Perf */
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/kernel/linux/linux-5.10/drivers/perf/
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
47 /* DDR Perf hardware feature */
52 unsigned int quirks; /* quirks needed for different DDR Perf core */
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
74 struct pmu pmu; member
94 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) in ddr_perf_filter_cap_get() argument
96 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D0001_linux_arch.patch7 Change-Id: I8c7b42f8858212fb4b2d56a871d3f4d5afc73954
9 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
11 --- a/arch/arm64/Kconfig
13 @@ -183,7 +183,6 @@ config ARM64
17 - select HOLES_IN_ZONE
21 @@ -1023,6 +1022,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
31 @@ -1148,7 +1150,7 @@ config XEN
35 - int
40 @@ -1182,15 +1184,6 @@ config UNMAP_KERNEL_AT_EL0
44 -config MITIGATE_SPECTRE_BRANCH_HISTORY
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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