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/third_party/mesa3d/.gitlab-ci/build/
Dgitlab-ci.yml2 .build-common:
3 extends: .build-rules
10 - _build/meson-logs/*.txt
11 - _build/meson-logs/strace
12 - shader-db
15 .build-linux:
16 extends: .build-common
23 - !reference [default, before_script]
24 - export PATH="/usr/lib/ccache:$PATH"
25 - export CCACHE_BASEDIR="$PWD"
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/third_party/mesa3d/
Dmeson_options.txt1 # Copyright © 2017-2019 Intel Corporation
31 'egl-native-platform',
41 'android-stub',
44 description : 'Build against android-stub',
55 'dri-drivers',
60 'dri-drivers-path',
66 'dri-search-path',
69 …: 'Locations to search for dri drivers, passed as colon separated list. Default: dri-drivers-path.'
72 'gallium-drivers',
83 'gallium-extra-hud',
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Dmeson.build1 # Copyright © 2017-2020 Intel Corporation
30 …default_options : ['buildtype=debugoptimized', 'b_ndebug=if-release', 'c_std=c11', 'cpp_std=c++14']
54 '-D__STDC_CONSTANT_MACROS',
55 '-D__STDC_FORMAT_MACROS',
56 '-D__STDC_LIMIT_MACROS',
57 '-DPACKAGE_VERSION="@0@"'.format(meson.project_version()),
58 '-DPACKAGE_BUGREPORT="https://gitlab.freedesktop.org/mesa/mesa/-/issues"',
63 with_moltenvk_dir = get_option('moltenvk-dir')
64 with_vulkan_icd_dir = get_option('vulkan-icd-dir')
65 with_tests = get_option('build-tests')
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D.pick_status.json31 "description": "pps: make pps-producer RT only on freedreno",
58 …"description": "tree-wide: Convert all usage of PIPE_(OS|ARCH|CC)_* to DETECT_(OS|ARCH|CC)_* by us…
67 …"description": "tree-wide: Convert all usage of #ifndef PIPE_(OS|ARCH|CC)_* to #if DETECT_(OS|ARCH…
76 …"description": "tree-wide: Convert all usage of #ifdef PIPE_(OS|ARCH|CC)_* to #if DETECT_(OS|ARCH|…
85 …"description": "tree-wide: Convert all usage of defined PIPE_(OS|ARCH|CC)_* to DETECT_(OS|ARCH|CC)…
94 …"description": "tree-wide: Convert all usage of defined(PIPE_(OS|ARCH|CC)_*) to DETECT_(OS|ARCH|CC…
220 …"description": "mesa/vbo: Replace the usage of cpu_has_sse4_1 with util_get_cpu_caps()->has_sse4_1…
256 "description": "microsoft/compiler: Delete now-unused memcpy lowering pass",
265 "description": "microsoft/clc: Optimize memcpys",
337 "description": "intel: Use common CONCAT/PASTE macros",
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/third_party/mesa3d/src/compiler/spirv/
Dnir_load_libclc.c2 * Copyright © 2020 Intel Corporation
27 #include "util/mesa-sha1.h"
42 #include "spirv-mesa3d-.spv.h"
46 #include "spirv64-mesa3d-.spv.h"
64 .sys_path = DYNAMIC_LIBCLC_PATH "spirv-mesa3d-.spv",
74 .sys_path = DYNAMIC_LIBCLC_PATH "spirv64-mesa3d-.spv",
97 open_clc_data(struct clc_data *clc, unsigned ptr_bit_size) in open_clc_data() argument
99 memset(clc, 0, sizeof(*clc)); in open_clc_data()
100 clc->file = get_libclc_file(ptr_bit_size); in open_clc_data()
101 clc->fd = -1; in open_clc_data()
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/third_party/mesa3d/docs/relnotes/
D21.3.0.rst1 Mesa 21.3.0 Release Notes / 2021-11-17
20 ---------------
24 a2753c09deef0ba14d35ae8a2ceff3fe5cd13698928c7bb62c2ec8736eb09ce1 mesa-21.3.0.tar.xz
28 ------------
30 - VK_EXT_color_write_enable on lavapipe
31 - GL_ARB_texture_filter_anisotropic in llvmpipe
32 - Anisotropic texture filtering in lavapipe
33 - VK_EXT_shader_atomic_float2 on Intel and RADV.
34 - VK_EXT_vertex_input_dynamic_state on RADV.
35 - VK_KHR_timeline_semaphore on lavapipe
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D22.2.0.rst1 Mesa 22.2.0 Release Notes / 2022-09-21
20 ---------------
24 b1f9c8fd08f2cae3adf83355bef4d2398e8025f44947332880f2d0066bdafa8c mesa-22.2.0.tar.xz
29 ------------
31 - WGL_ARB_create_context_robustness
33 - d3d12 ARB_robust_buffer_access_behavior
35 - VK_EXT_robustness2 for lavapipe
37 - VK_EXT_image_2d_view_of_3d on RADV
39 - zink and d3d12 GL_EXT_memory_object_win32 and GL_EXT_semaphore_win32 support
41 - vertexAttributeInstanceRateZeroDivisor support for lavapipe
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D21.0.0.rst1 Mesa 21.0.0 Release Notes / 2021-03-11
20 ---------------
24 e6204e98e6a8d77cf9dc5d34f99dd8e3ef7144f3601c808ca0dd26ba522e0d84 mesa-21.0.0.tar.xz
28 ------------
30 - GL_EXT_demote_to_helper_invocation on radeonsi
32 - GL_NV_compute_shader_derivatives on radeonsi
34 - EGL_MESA_platform_xcb
36 - Removed GL_NV_point_sprite for classic swrast.
38 - driconf: remove glx_disable_oml_sync_control, glx_disable_sgi_video_sync, and glx_disable_ext_buf…
40 - Removed support for loading DRI drivers older than Mesa 8.0, including all DRI1 support
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D22.1.0.rst1 Mesa 22.1.0 Release Notes / 2022-05-18
20 ---------------
24 df6270c1371eaa2aa6eb65b95cbbb2a98b14fa4b7ba0ed45e4ca2fd32df60477 mesa-22.1.0.tar.xz
28 ------------
30 - d3d12 GL4.2
31 - GL_NV_pack_subimage
32 - VK_EXT_depth_clip_control on lavapipe and RADV
33 - Vulkan 1.3 support on lavapipe
34 - VK_EXT_graphics_pipeline_library on lavapipe
35 - VK_EXT_primitives_generated_query on lavapipe
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D21.1.0.rst1 Mesa 21.1.0 Release Notes / 2021-05-05
20 ---------------
24 0128f10e22970d3aed3d1034003731f94623015cd9797c07151417649c1b1ff8 mesa-21.1.0.tar.xz
28 ------------
30 - VK_KHR_workgroup_memory_explicit_layout on Intel, RADV
32 - DRM format modifiers for AMD.
34 - VK_KHR_zero_initialize_workgroup_memory on Intel, RADV
36 - Zink exposes GL 4.6 and ES 3.1
38 - GL_EXT_depth_bounds_test on softpipe, zink
40 - GL_EXT_texture_filter_minmax on nvc0 (gm200+)
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D22.0.0.rst1 Mesa 22.0.0 Release Notes / 2022-03-09
20 ---------------
24 e6c41928b5b9917485bd67cec22d15e62cad7a358bf4c711a647979987601250 mesa-22.0.0.tar.xz
28 ------------
30 - lavapipe,radv,anv KHR_dynamic_rendering
31 - radv EXT_image_view_min_lod
32 - VK_KHR_synchronization2 on RADV.
33 - OpenSWR has been moved to the Amber branch
34 - radeonsi, zink ARB_sparse_texture
35 - d3d12 GLES3.1 (shader storage buffers, images, compute, indirect draw, draw params, ARB_framebuff…
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D21.2.0.rst1 Mesa 21.2.0 Release Notes / 2021-08-04
20 ---------------
24 0cb3c802f4b8e7699b1602c08c29d06a4d532ab5b8f7a64676c4ca6bb8f4d426 mesa-21.2.0.tar.xz
28 ------------
30 - zink supports GL_ARB_texture_filter_minmax, GL_ARB_shader_clock
32 - VK_EXT_provoking_vertex on RADV.
34 - VK_EXT_extended_dynamic_state2 on RADV.
36 - VK_EXT_global_priority_query on RADV.
38 - VK_EXT_physical_device_drm on RADV.
40 - VK_KHR_shader_subgroup_uniform_control_flow on Intel and RADV.
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/third_party/mesa3d/ohos/
Ddependency_inputs.gni41 "../bin/khronos-update.py",
42 "../bin/meson-cmd-extract.py",
43 "../bin/meson-options.py",
46 "../bin/perf-annotate-jit.py",
47 "../bin/pick-ui.py",
50 "../bin/symbols-check.py",
51 "../bin/update-android-headers.sh",
58 "../build-support/conftest.dyn",
59 "../build-support/conftest.map",
172 "../include/android_stub/system/graphics-base-v1.0.h",
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/third_party/mesa3d/src/intel/compiler/
Dintel_clc.c2 * Copyright © 2021 Intel Corporation
27 #include "compiler/clc/clc.h"
33 #include "util/mesa-sha1.h"
53 compiler->devinfo->pci_device_id); in get_disk_cache()
54 assert(len == sizeof(renderer) - 2); in get_disk_cache()
59 fprintf(stderr, "Failed to find build-id\n"); in get_disk_cache()
65 fprintf(stderr, "build-id too short. It needs to be a SHA\n"); in get_disk_cache()
134 fprintf(fp, "%s." #field " = " fmt ",\n", pad, cs_prog_data->field) in print_cs_prog_data_fields()
138 cs_prog_data->field ? "true" : "false") in print_cs_prog_data_fields()
141 assert(cs_prog_data->base.stage == MESA_SHADER_COMPUTE); in print_cs_prog_data_fields()
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/third_party/mesa3d/src/mesa/x86/
Dassyntax.h58 * Floating-point:
66 * [support for Intel syntax added by Josh Vanderhoof, 1999]
90 /* Assume we write code for 32-bit protected mode! */
137 /* Floating-point Stack */
199 /* Floating-point Stack */
296 /* 'as -aout' on FreeBSD doesn't have .balign */
342 /* Reg indirect Base + Index + Displacement - this is mainly for 16-bit mode
412 #define CLC CHOICE(clc, clc, clc) macro
811 /* Intel style assemblers. */
1039 /* Reg indirect Base + Index + Displacement - this is mainly for 16-bit mode
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrInfo.td1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
28 // Unary and binary operator instructions that set EFLAGS as a side-effect.
38 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
87 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
94 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
96 def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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DX86SchedSandyBridge.td1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
19 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
21 // FIXME: Identify instructions that aren't a single fused micro-op.
27 // Based on the LSD (loop-stream detector) queue size.
37 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
53 // Many micro-ops are capable of issuing on multiple ports.
82 // Instructions with folded loads are usually micro-fused, so they only appear
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DX86SchedSkylakeClient.td1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 // All x86 instructions are modeled as a single micro-op, and SKylake can
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
49 // Many micro-ops are capable of issuing on multiple ports.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
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DX86SchedBroadwell.td1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
49 // Many micro-ops are capable of issuing on multiple ports.
87 // Instructions with folded loads are usually micro-fused, so they only appear
88 // as two micro-ops when queued in the reservation station.
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DX86SchedHaswell.td1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
20 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
27 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
37 // Haswell can issue micro-ops to 8 different ports in one cycle.
54 // Many micro-ops are capable of issuing on multiple ports.
92 // Instructions with folded loads are usually micro-fused, so they only appear
93 // as two micro-ops when queued in the reservation station.
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DX86SchedSkylakeServer.td1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 // All x86 instructions are modeled as a single micro-op, and SKylake can
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
49 // Many micro-ops are capable of issuing on multiple ports.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
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/third_party/rust/crates/memchr/bench/data/sliceslice/
Di386-notutf8.txt1 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986
3 Intel Corporation makes no warranty for the use of its products and
7 Intel retains the right to make changes to these specifications at any
13 The following are trademarks of Intel Corporation and may only be used to
14 identify Intel Products:
18 Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,
22 MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,
23 PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80,
26 suffix, 4-SITE.
32 Additional copies of this manual or other Intel literature may be obtained
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Di386.txt1 INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986
3 Intel Corporation makes no warranty for the use of its products and
7 Intel retains the right to make changes to these specifications at any
13 The following are trademarks of Intel Corporation and may only be used to
14 identify Intel Products:
18 Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,
22 MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,
23 PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80,
26 suffix, 4-SITE.
32 Additional copies of this manual or other Intel literature may be obtained
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