| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
164 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
165 usb2->base.np = np; in tegra186_usb2_lane_probe()
167 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra186_usb2_lane_probe()
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| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
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| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
297 return -ENODEV; in tegra124_usb3_save_context()
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| /kernel/linux/linux-6.6/drivers/phy/tegra/ |
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
309 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
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| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
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| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
297 return -ENODEV; in tegra124_usb3_save_context()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | parade,ps8622.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 - parade,ps8622
16 - parade,ps8625
21 lane-count:
26 use-external-pwm:
30 reset-gpios:
34 sleep-gpios:
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/ |
| D | cros-ec-anx7688.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * CrOS EC ANX7688 HDMI->DP bridge driver
58 if (!anx->filter) in cros_ec_anx7688_bridge_mode_fixup()
61 /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */ in cros_ec_anx7688_bridge_mode_fixup()
62 ret = regmap_bulk_read(anx->regmap, ANX7688_DP_BANDWIDTH_REG, regs, 2); in cros_ec_anx7688_bridge_mode_fixup()
64 DRM_ERROR("Failed to read bandwidth/lane count\n"); in cros_ec_anx7688_bridge_mode_fixup()
72 DRM_ERROR("Invalid bandwidth/lane count (%02x/%d)\n", dpbw, in cros_ec_anx7688_bridge_mode_fixup()
81 requiredbw = mode->clock * 8 * 3; in cros_ec_anx7688_bridge_mode_fixup()
87 DRM_ERROR("Bandwidth/lane count are 0, not rejecting modes\n"); in cros_ec_anx7688_bridge_mode_fixup()
100 struct device *dev = &client->dev; in cros_ec_anx7688_bridge_probe()
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| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-devices-platform-kunpeng_hccs | 9 contains read-only attributes exposing some summarization
19 lane (bool).
20 crc_err_cnt: (RO) total CRC err count for all ports on this
32 contains read-only attributes exposing some summarization
43 lane (bool).
44 crc_err_cnt: (RO) total CRC err count for all ports on this
60 contains read-only attributes exposing information about
63 HCCS port belongs. For example, X ranges from to 'n - 1' if the
73 type: (RO) port type (string), e.g. HCCS-v1 -> H32
74 lane_mode: (RO) the lane mode of this port (string), e.g. x8
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| /kernel/linux/linux-6.6/drivers/net/ethernet/sfc/falcon/ |
| D | txc43128_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/sfc/falcon/ |
| D | txc43128_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/ |
| D | dp_panel.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
72 * is_link_rate_valid() - validates the link rate
86 * dp_link_is_lane_count_valid() - validates the lane count
87 * @lane_count: lane count requested by the sink
89 * Returns true if the requested lane count is supported.
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/ |
| D | dp_panel.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
77 * is_link_rate_valid() - validates the link rate
91 * dp_link_is_lane_count_valid() - validates the lane count
92 * @lane_count: lane count requested by the sink
94 * Returns true if the requested lane count is supported.
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_training_fixed_vs_pe_retimer.c | 42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
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| D | link_dp_training_8b_10b.c | 36 link->ctx->logger
46 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_cr_training_aux_rd_interval()
72 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
100 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set; in decide_8b_10b_training_settings()
101 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; in decide_8b_10b_training_settings()
102 lt_settings->link_settings.link_rate = link_setting->link_rate; in decide_8b_10b_training_settings()
103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
107 * path_mode->display_path) ? in decide_8b_10b_training_settings()
111 lt_settings->link_settings.link_spread = link->dp_ss_off ? in decide_8b_10b_training_settings()
113 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting); in decide_8b_10b_training_settings()
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| /kernel/linux/linux-6.6/include/linux/phy/ |
| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
78 * Flag indicating, whether or not reconfigure lane count to
88 * and pre-emphasis to requested values. Only lanes specified
|
| /kernel/linux/linux-5.10/include/linux/phy/ |
| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
31 * lane 0, used for the transmissions on main link.
41 * to be used by particular lanes. One value per lane.
42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
52 * used by particular lanes. One value per lane.
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
78 * Flag indicating, whether or not reconfigure lane count to
88 * and pre-emphasis to requested values. Only lanes specified
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
43 * IOSF-SB port.
46 * houses a common lane part which contains the PLL and other common
47 * logic. CH0 common lane also contains the IOSF-SB logic for the
57 * each spline is made up of one Physical Access Coding Sub-Layer
62 * Additionally the PHY also contains an AUX lane with AUX blocks
68 * Generally on VLV/CHV the common lane corresponds to the pipe and
101 * ---------------------------------
104 * |---------------|---------------| Display PHY
106 * |-------|-------|-------|-------|
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
39 * IOSF-SB port.
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * each spline is made up of one Physical Access Coding Sub-Layer
58 * Additionally the PHY also contains an AUX lane with AUX blocks
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
97 * ---------------------------------
100 * |---------------|---------------| Display PHY
102 * |-------|-------|-------|-------|
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| D | intel_dp_link_training.c | 2 * Copyright © 2008-2015 Intel Corporation
58 int lane; in intel_dp_get_adjust_train() local
62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
63 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); in intel_dp_get_adjust_train()
64 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); in intel_dp_get_adjust_train()
67 preemph_max = intel_dp->preemph_max(intel_dp); in intel_dp_get_adjust_train()
68 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
77 voltage_max = intel_dp->voltage_max(intel_dp); in intel_dp_get_adjust_train()
78 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
85 for (lane = 0; lane < 4; lane++) in intel_dp_get_adjust_train()
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| /kernel/linux/linux-6.6/drivers/edac/ |
| D | thunderx_edac.c | 8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
56 while (descr->type && descr->mask && descr->descr) { in decode_register()
57 if (reg & descr->mask) { in decode_register()
59 descr->type == ERR_CORRECTED ? in decode_register()
61 descr->descr); in decode_register()
63 size -= ret; in decode_register()
71 return (data >> pos) & ((1 << width) - 1); in get_bits()
127 .descr = "Single-bit ECC error",
137 .descr = "Double-bit ECC error",
142 .descr = "Non-existent memory write",
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | thunderx_edac.c | 8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
56 while (descr->type && descr->mask && descr->descr) { in decode_register()
57 if (reg & descr->mask) { in decode_register()
59 descr->type == ERR_CORRECTED ? in decode_register()
61 descr->descr); in decode_register()
63 size -= ret; in decode_register()
71 return (data >> pos) & ((1 << width) - 1); in get_bits()
127 .descr = "Single-bit ECC error",
137 .descr = "Double-bit ECC error",
142 .descr = "Non-existent memory write",
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | ps8622.txt | 1 ps8622-bridge bindings
4 - compatible: "parade,ps8622" or "parade,ps8625"
5 - reg: first i2c address of the bridge
6 - sleep-gpios: OF device-tree gpio specification for PD_ pin.
7 - reset-gpios: OF device-tree gpio specification for RST_ pin.
10 - lane-count: number of DP lanes to use
11 - use-external-pwm: backlight will be controlled by an external PWM
12 - video interfaces: Device node can contain video interface port
15 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
18 lvds-bridge@48 {
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
82 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
84 if (!dp->force_hpd) in analogix_dp_detect_hpd()
85 return -ETIMEDOUT; in analogix_dp_detect_hpd()
92 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
97 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
98 return -EINVAL; in analogix_dp_detect_hpd()
101 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
111 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
113 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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