| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| D | cache.json | 105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
120 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | metrics.json | 89 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
103 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
117 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
131 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
145 …ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives a…
152 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | metrics.json | 4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC…
15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp…
61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - …
101 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
115 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
122 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
129 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
136 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
143 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 111 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
114 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/kvm/mmu/ |
| D | tdp_iter.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Recalculates the pointer to the SPTE for the current GFN and level and
13 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
14 SHADOW_PT_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
15 iter->old_spte = READ_ONCE(*iter->sptep); in tdp_iter_refresh_sptep()
18 static gfn_t round_gfn_for_level(gfn_t gfn, int level) in round_gfn_for_level() argument
20 return gfn & -KVM_PAGES_PER_HPAGE(level); in round_gfn_for_level()
24 * Sets a TDP iterator to walk a pre-order traversal of the paging structure
33 iter->next_last_level_gfn = next_last_level_gfn; in tdp_iter_start()
34 iter->yielded_gfn = iter->next_last_level_gfn; in tdp_iter_start()
[all …]
|
| /kernel/linux/linux-5.10/kernel/rcu/ |
| D | tree.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions.
38 * Definition for node within the RCU grace-period-detection hierarchy.
44 unsigned long gp_seq; /* Track rsp->gp_seq. */
55 /* Per-GP initial value for qsmask. */
56 /* Initialized from ->qsmaskinitnext at the */
59 unsigned long ofl_seq; /* CPU-hotplug operation sequence count. */
65 /* Per-GP initial values for expmask. */
66 /* Initialized from ->expmaskinitnext at the */
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/kvm/mmu/ |
| D | tdp_iter.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Recalculates the pointer to the SPTE for the current GFN and level and
14 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
15 SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
16 iter->old_spte = kvm_tdp_mmu_read_spte(iter->sptep); in tdp_iter_refresh_sptep()
25 iter->yielded = false; in tdp_iter_restart()
26 iter->yielded_gfn = iter->next_last_level_gfn; in tdp_iter_restart()
27 iter->level = iter->root_level; in tdp_iter_restart()
29 iter->gfn = gfn_round_for_level(iter->next_last_level_gfn, iter->level); in tdp_iter_restart()
32 iter->valid = true; in tdp_iter_restart()
[all …]
|
| /kernel/linux/linux-6.6/kernel/rcu/ |
| D | tree.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions.
43 * Definition for node within the RCU grace-period-detection hierarchy.
49 unsigned long gp_seq; /* Track rsp->gp_seq. */
60 /* Per-GP initial value for qsmask. */
61 /* Initialized from ->qsmaskinitnext at the */
68 /* Per-GP initial values for expmask. */
69 /* Initialized from ->expmaskinitnext at the */
80 int grplo; /* lowest-numbered CPU here. */
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
24 - qcom,sc7180-llcc
25 - qcom,sdm845-llcc
29 - description: LLCC base register region
[all …]
|
| /kernel/linux/linux-5.10/fs/xfs/libxfs/ |
| D | xfs_btree.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2000-2001,2005 Silicon Graphics, Inc.
29 * The in-core btree key. Overlapping btrees actually store two keys
53 * This nonsense is to make -wlint happy.
82 #define XFS_BB_ALL_BITS ((1 << XFS_BB_NUM_BITS) - 1)
84 #define XFS_BB_ALL_BITS_CRC ((1 << XFS_BB_NUM_BITS_CRC) - 1)
90 XFS_STATS_INC_OFF((cur)->bc_mp, (cur)->bc_statoff + __XBTS_ ## stat)
92 XFS_STATS_ADD_OFF((cur)->bc_mp, (cur)->bc_statoff + __XBTS_ ## stat, val)
117 /* update last record information */
123 /* records in block/level */
[all …]
|
| D | xfs_btree.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc.
48 /* Ensure we asked for crc for crc-only magics. */ in xfs_btree_magic()
61 int level, in __xfs_btree_check_lblock() argument
64 struct xfs_mount *mp = cur->bc_mp; in __xfs_btree_check_lblock()
65 xfs_btnum_t btnum = cur->bc_btnum; in __xfs_btree_check_lblock()
66 int crc = xfs_sb_version_hascrc(&mp->m_sb); in __xfs_btree_check_lblock()
69 if (!uuid_equal(&block->bb_u.l.bb_uuid, &mp->m_sb.sb_meta_uuid)) in __xfs_btree_check_lblock()
71 if (block->bb_u.l.bb_blkno != in __xfs_btree_check_lblock()
72 cpu_to_be64(bp ? bp->b_bn : XFS_BUF_DADDR_NULL)) in __xfs_btree_check_lblock()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/mm/ |
| D | numaperf.rst | 20 +------------------+ +------------------+
21 | Compute Node 0 +-----+ Compute Node 1 |
23 +--------+---------+ +--------+---------+
25 +--------+---------+ +--------+---------+
27 +------------------+ +--------+---------+
35 performance when accessing a given memory target. Each initiator-target
47 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
48 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
50 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
51 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/mm/ |
| D | numaperf.rst | 21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/ath/ath5k/ |
| D | ani.c | 33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
63 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
70 * and ath9k use only the last two levels, making this in ath5k_ani_set_noise_immunity_level()
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/ath/ath5k/ |
| D | ani.c | 33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
63 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
70 * and ath9k use only the last two levels, making this in ath5k_ani_set_noise_immunity_level()
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/Documentation/ |
| D | itrace.txt | 9 of aux-output (refer to perf record)
12 f synthesize first level cache events
13 m synthesize last level cache events
18 l synthesize last branch entries (use with i or x)
19 L synthesize last branch entries on existing event records
23 The default is all events i.e. the same as --itrace=ibxwpe,
24 except for perf script where it is --itrace=ce
38 Also the number of last branch entries (default 64, max. 1024) for
43 large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
48 --itrace=i0nss1000000
[all …]
|
| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
[all …]
|
| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_vm.c | 28 #include <linux/dma-fence-array.h>
31 #include <linux/dma-buf.h>
62 #define START(node) ((node)->start)
63 #define LAST(node) ((node)->last) macro
66 START, LAST, static, amdgpu_vm_it)
69 #undef LAST
72 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
88 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
90 * an MMU notifier runs in reclaim-FS context.
94 mutex_lock(&vm->eviction_lock); in amdgpu_vm_eviction_lock()
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/Documentation/ |
| D | itrace.txt | 10 of aux-output (refer to perf record)
15 f synthesize first level cache events
16 m synthesize last level cache events
22 l synthesize last branch entries (use with i or x)
23 L synthesize last branch entries on existing event records
27 Z prefer to ignore timestamps (so-called "timeless" decoding)
29 The default is all events i.e. the same as --itrace=iybxwpe,
30 except for perf script where it is --itrace=ce
44 Also the number of last branch entries (default 64, max. 1024) for
49 large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/ |
| D | common-and-microarch.json | 9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
[all …]
|
| /kernel/linux/linux-6.6/fs/xfs/scrub/ |
| D | bitmap.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2018-2023 Oracle. All Rights Reserved.
25 /* Last set bit of this interval. */
28 /* Last set bit of this subtree. Do not touch this. */
34 #define START(node) ((node)->bn_start)
35 #define LAST(node) ((node)->bn_last) macro
39 * forward-declare them anyway for clarity.
49 uint64_t last);
53 uint64_t last);
56 __bn_subtree_last, START, LAST, static inline, xbitmap_tree) in INTERVAL_TREE_DEFINE() argument
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | amd-pstate.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/amd-pstate.h
21 * AMD P-state INTERFACE *
36 * struct amd_cpudata - private CPU data for AMD P-State
42 * @nominal_perf: the maximum sustained performance level of the processor,
44 * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
46 * @lowest_perf: the absolute lowest performance level of the processor
51 * @cur: Difference of Aperf/Mperf/tsc count between last and current sample
52 * @prev: Last Aperf/Mperf/tsc count value read from register
57 * AMD P-State driver supports preferred core featue.
[all …]
|
| /kernel/linux/linux-6.6/drivers/md/bcache/ |
| D | btree.c | 1 // SPDX-License-Identifier: GPL-2.0
21 * All configuration is done via sysfs; see Documentation/admin-guide/bcache.rst.
100 (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
104 #define insert_lock(s, b) ((b)->level <= (s)->lock)
109 return ((void *) btree_bset_first(b)) + b->written * block_bytes(b->c->cache); in write_block()
115 if (b->level && b->keys.nsets) in bch_btree_init_next()
116 bch_btree_sort(&b->keys, &b->c->sort); in bch_btree_init_next()
118 bch_btree_sort_lazy(&b->keys, &b->c->sort); in bch_btree_init_next()
120 if (b->written < btree_blocks(b)) in bch_btree_init_next()
121 bch_bset_init_next(&b->keys, write_block(b), in bch_btree_init_next()
[all …]
|
| /kernel/linux/linux-6.6/fs/xfs/libxfs/ |
| D | xfs_btree.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc.
49 /* Ensure we asked for crc for crc-only magics. */ in xfs_btree_magic()
61 * on x86-64. Yes, gcc-11 fails to inline them, and explicit inlining of these
69 int level, in xfs_btree_check_lblock_siblings() argument
81 if (level >= 0) { in xfs_btree_check_lblock_siblings()
82 if (!xfs_btree_check_lptr(cur, sibling, level + 1)) in xfs_btree_check_lblock_siblings()
96 int level, in xfs_btree_check_sblock_siblings() argument
108 if (level >= 0) { in xfs_btree_check_sblock_siblings()
109 if (!xfs_btree_check_sptr(cur, sibling, level + 1)) in xfs_btree_check_sblock_siblings()
[all …]
|