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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ddr/
Dlpddr2.txt1 * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
4 - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
5 "jedec,lpddr2-s4"
7 "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
9 "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
11 "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
13 - density : <u32> representing density in Mb (Mega bits)
15 - io-width : <u32> representing bus width. Possible values are 8, 16, and 32
21 These values shall be obtained from the device data-sheet.
22 - tRRD-min-tck
[all …]
Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
11 data-sheet of the device for a given speed-bin. All these properties are
13 a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
14 - tRCD
15 - tWR
16 - tRAS-min
17 - tRRD
[all …]
Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
3 The structures are based on LPDDR2 and extended where needed.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
[all …]
Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Delpida_ecb240abacn.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 elpida_ECB240ABACN: lpddr2 {
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Delpida_ecb240abacn.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 elpida_ECB240ABACN: lpddr2 {
8 compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dof_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
26 * default min timings provided by JEDEC.
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
41 ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin); in of_get_min_tck()
42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
44 ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); in of_get_min_tck()
[all …]
Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
96 * LPDDR2 related defines
143 * Structure for timings from the LPDDR2 datasheet
205 * Structure for information about LPDDR2 chip. All parameters are
207 * -ENOENT if info unavailable.
221 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
97 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
98 This driver takes care of only LPDDR2 memories presently. The
[all …]
Demif.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * struct emif_data - Per device static data for driver's use
36 * @temperature_level: Maximum temperature of LPDDR2 devices attached
37 * to this EMIF - read from MR4 register. If there
42 * @base: base address of memory-mapped IO registers.
46 * frequencies, to avoid re-calculating them on
79 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show()
80 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
83 regs->freq/1000000); in do_emif_regdump_show()
85 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); in do_emif_regdump_show()
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Demif_plat.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Low power modes - EMIF_PWR_MGMT_CTRL */
23 * EMIF4D - Used in OMAP4
24 * EMIF4D5 - Used in OMAP5
31 * ATTILAPHY - Used in OMAP4
32 * INTELLIPHY - Used in OMAP5
44 * struct ddr_device_info - All information about the DDR device except AC
46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
50 * chip-select(CS1) of this EMIF instance
52 * chip-select or whether it's a single one for both
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Demif_plat.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Low power modes - EMIF_PWR_MGMT_CTRL */
23 * EMIF4D - Used in OMAP4
24 * EMIF4D5 - Used in OMAP5
31 * ATTILAPHY - Used in OMAP4
32 * INTELLIPHY - Used in OMAP5
44 * struct ddr_device_info - All information about the DDR device except AC
46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
50 * chip-select(CS1) of this EMIF instance
52 * chip-select or whether it's a single one for both
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
96 * LPDDR2 related defines
123 * Structure for timings from the LPDDR2 datasheet
174 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
42 LP-DDR memories.
53 Used to configure the EBI (external bus interface) when the device-
70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
77 tags and way-select latencies of RAM access. This driver provides a
[all …]
Dof_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
26 * default min timings provided by JEDEC.
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
41 ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin); in of_get_min_tck()
42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
44 ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); in of_get_min_tck()
[all …]
Demif.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * struct emif_data - Per device static data for driver's use
36 * @temperature_level: Maximum temperature of LPDDR2 devices attached
37 * to this EMIF - read from MR4 register. If there
42 * @base: base address of memory-mapped IO registers.
47 * frequencies, to avoid re-calculating them on
82 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show()
83 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
86 regs->freq/1000000); in do_emif_regdump_show()
88 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); in do_emif_regdump_show()
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/memory-devices/
Dti-emif.rst1 .. SPDX-License-Identifier: GPL-2.0
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
31 This driver takes care of only LPDDR2 memories presently. The
32 functions of the driver includes re-configuring AC timing
41 - DDR device details: 'struct ddr_device_info'
42 - Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
43 - Custom configurations: customizable policy options through
45 - IP revision
46 - PHY type
53 - freq_pre_notify_handling()
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/memory-devices/
Dti-emif.rst1 .. SPDX-License-Identifier: GPL-2.0
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
31 This driver takes care of only LPDDR2 memories presently. The
32 functions of the driver includes re-configuring AC timing
41 - DDR device details: 'struct ddr_device_info'
42 - Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
43 - Custom configurations: customizable policy options through
45 - IP revision
46 - PHY type
53 - freq_pre_notify_handling()
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
206 struct emc_timing *timings; member
221 /* protect shared rate-change code path */
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
264 timing = &emc->timings[i]; in tegra_emc_find_timing()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
39 const: nvidia,tegra30-mc
47 clock-names:
[all …]
Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
39 const: nvidia,tegra30-mc
47 clock-names:
[all …]
Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]

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