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/third_party/pulseaudio/src/pulsecore/
Dmcalign.c4 Copyright 2004-2006 Lennart Poettering
34 size_t base; member
38 pa_mcalign *pa_mcalign_new(size_t base) { in pa_mcalign_new() argument
40 pa_assert(base); in pa_mcalign_new()
44 m->base = base; in pa_mcalign_new()
45 pa_memchunk_reset(&m->leftover); in pa_mcalign_new()
46 pa_memchunk_reset(&m->current); in pa_mcalign_new()
54 if (m->leftover.memblock) in pa_mcalign_free()
55 pa_memblock_unref(m->leftover.memblock); in pa_mcalign_free()
57 if (m->current.memblock) in pa_mcalign_free()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp1 //===----- RISCVMergeBaseOffset.cpp - Optimise address calculations ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Merge the offset of address calculation into the offset field
20 // 1) The offset field in the base of global address lowering sequence is zero.
24 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "riscv-merge-base-offset"
36 #define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
67 INITIALIZE_PASS(RISCVMergeBaseOffsetOpt, "riscv-merge-base-offset",
86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) in detectLuiAddiGlobal()
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/third_party/mindspore/mindspore-src/source/tests/st/networks/models/fasterrcnn/src/utils/
Dconfig.py7 # http://www.apache.org/licenses/LICENSE-2.0
57 config: dict-like object
74 BASE = "__BASE__"
75 assert os.path.splitext(file_path)[-1] in [".yaml", ".yml"], f"[{file_path}] not yaml format."
79 if BASE in cfg_default:
83 base_yamls = list(cfg_default[BASE])
95 del cfg_default[BASE]
132 def merge_config(config, base): argument
133 """Merge config"""
134 new = deepcopy(base)
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/third_party/mesa3d/
D.gitlab-ci.yml3 MESA_TEMPLATES_COMMIT: &ci-templates-commit 290b79e0e78eab67a83766f4e9691be554fc4afd
4 CI_PRE_CLONE_SCRIPT: |-
5 set -o xtrace
6 …wget -q -O download-git-cache.sh ${CI_PROJECT_URL}/-/raw/${CI_COMMIT_SHA}/.gitlab-ci/download-git-…
7 bash download-git-cache.sh
8 rm download-git-cache.sh
12 # per-pipeline artifact storage on MinIO
14 # per-job artifact storage on MinIO
17 PIGLIT_REPLAY_REFERENCE_IMAGES_BASE: "${MINIO_HOST}/mesa-tracie-results/$FDO_UPSTREAM_REPO"
28 …- echo -e "\e[0Ksection_start:$(date +%s):unset_env_vars_section[collapsed=true]\r\e[0KUnsetting v…
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/third_party/typescript/scripts/
Dupdate-experimental-branches.mjs2 import { runSequence } from "./run-sequence.mjs";
4 // The first is used by bot-based kickoffs, the second by automatic triggers
8 …* This program should be invoked as `node ./scripts/update-experimental-branches <GithubAccessToke…
9 …* TODO: the following is racey - if two experiment-enlisted PRs trigger simultaneously and witness…
35 ["git", ["fetch", "-fu", "origin", "main:main"]],
43 // PR number rather than branch name - lookup info
45 … // GH calculates the rebaseable-ness of a PR into its target, so we can just use that here
52 …s configured as an experiment, and currently has rebase conflicts with main - please rebase onto m…
61 … ["git", ["push", "-f", "-u", "fork", `${num}`]], // Keep a rebased copy of this branch in our fork
73 ["git", ["checkout", "-b", "experimental"]],
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Dopen-cherry-pick-pr.mjs2 import { runSequence } from "./run-sequence.mjs";
24 ["git", ["rev-parse", "HEAD"]]
27 ["git", ["log", "-1", `--pretty="%aN <%aE>"`]]
36 …if (inputPR.base.repo.git_url !== `git:github.com/microsoft/TypeScript` && inputPR.base.repo.git_u…
38 …["git", ["remote", "add", "nonlocal", inputPR.base.repo.git_url.replace(/^git:(?:\/\/)?/, "https:/…
42 const baseBranchName = inputPR.base.ref;
47 …og", `${remoteName}/${baseBranchName}..${currentSha.trim()}`, `--pretty="%h %s%n%b"`, "--reverse"]]
49 logText = `Cherry-pick PR #${process.env.SOURCE_ISSUE} into ${process.env.TARGET_BRANCH}
54 …const mergebase = runSequence([["git", ["merge-base", `${remoteName}/${baseBranchName}`, currentSh…
56 ["git", ["checkout", "-b", "temp-branch"]],
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/third_party/protobuf/java/util/src/main/java/com/google/protobuf/util/
DFieldMaskUtil.java1 // Protocol Buffers - Google's data interchange format
3 // https://developers.google.com/protocol-buffers/
33 import static com.google.common.base.Preconditions.checkArgument;
35 import com.google.common.base.CaseFormat;
36 import com.google.common.base.Joiner;
37 import com.google.common.base.Optional;
38 import com.google.common.base.Splitter;
64 // TODO(xiaofeng): Consider using com.google.common.base.Joiner here instead. in toString()
86 // TODO(xiaofeng): Consider using com.google.common.base.Splitter here instead. in fromString()
96 // TODO(xiaofeng): Consider using com.google.common.base.Splitter here instead. in fromString()
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/third_party/mbedtls/scripts/mbedtls_dev/
Dbignum_mod_raw.py3 # SPDX-License-Identifier: Apache-2.0
9 # http://www.apache.org/licenses/LICENSE-2.0
25 #pylint: disable=abstract-method, too-few-public-methods
29 # BEGIN MERGE SLOT 1
31 # END MERGE SLOT 1
33 # BEGIN MERGE SLOT 2
38 symbol = "-"
44 def arguments(self) -> List[str]:
50 def result(self) -> List[str]:
51 result = (self.int_a - self.int_b) % self.int_n
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/third_party/mindspore/mindspore-src/source/mindspore/core/
DCMakeLists.txt9 string(REPLACE " -Werror " " " CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}")
10 …string(REPLACE " -fvisibility=hidden" " -fvisibility=default" CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}")
14 string(REPLACE "-fno-rtti" "" CMAKE_C_FLAGS ${CMAKE_C_FLAGS})
15 string(REPLACE "-fno-exceptions" "" CMAKE_C_FLAGS ${CMAKE_C_FLAGS})
18 string(REPLACE "-fno-rtti" "" CMAKE_CXX_FLAGS ${CMAKE_CXX_FLAGS})
19 string(REPLACE "-fno-exceptions" "" CMAKE_CXX_FLAGS ${CMAKE_CXX_FLAGS})
32 include(${TOP_DIR}/mindspore/lite/cmake/merge.cmake)
34 … merge_files(${CMAKE_CURRENT_SOURCE_DIR}/ops/ ${CMAKE_BINARY_DIR}/merge/mindspore/core ops_merge
37 …merge_files(${CMAKE_CURRENT_SOURCE_DIR}/ops/ ${CMAKE_BINARY_DIR}/merge/mindspore/core ops_merge "")
40 "${CMAKE_BINARY_DIR}/merge/mindspore/core/ops_merge*.cc")
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DMergeICmps.cpp1 //===- MergeICmps.cpp - Optimize chains of integer comparisons ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // - There are less jumps, and therefore less opportunities for mispredictions
17 // and I-cache misses.
18 // - Code size is smaller, both because jumps are removed and because the
19 // encoding of a 2*n byte compare is smaller than that of two n-byte
40 // Which will later be expanded (ExpandMemCmp) as a single 8-bytes icmp.
42 //===----------------------------------------------------------------------===//
72 return LI->isSimple(); in isSimpleLoadOrStore()
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/third_party/mesa3d/src/compiler/nir/
Dnir_lower_io_to_vector.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
44 /* This handling of dual-source blending might not be correct when more than in get_slot()
47 return var->data.location + var->data.index; in get_slot()
54 if (nir_is_arrayed_io(var, shader->info.stage)) { in get_per_vertex_type()
55 assert(glsl_type_is_array(var->type)); in get_per_vertex_type()
57 *num_vertices = glsl_get_length(var->type); in get_per_vertex_type()
58 return glsl_get_array_element(var->type); in get_per_vertex_type()
62 return var->type; in get_per_vertex_type()
84 if (a->data.compact || b->data.compact) in variables_can_merge()
87 if (a->data.per_view || b->data.per_view) in variables_can_merge()
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/third_party/mesa3d/src/gallium/drivers/virgl/
Dvirgl_transfer_queue.c7 * on the rights to use, copy, modify, merge, publish, distribute, sub
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
27 #include "virtio-gpu/virgl_protocol.h"
58 switch (xfer->base.resource->target) { in transfer_dim()
75 if (box->width > 0) { in box_min_max()
76 *min = box->x; in box_min_max()
77 *max = box->x + box->width; in box_min_max()
79 *max = box->x; in box_min_max()
80 *min = box->x + box->width; in box_min_max()
84 if (box->height > 0) { in box_min_max()
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Dvirgl_streamout.c7 * on the rights to use, copy, modify, merge, publish, distribute, sub
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
27 #include "virtio-gpu/virgl_protocol.h"
45 t->base.reference.count = 1; in virgl_create_so_target()
46 t->base.context = ctx; in virgl_create_so_target()
47 pipe_resource_reference(&t->base.buffer, buffer); in virgl_create_so_target()
48 t->base.buffer_offset = buffer_offset; in virgl_create_so_target()
49 t->base.buffer_size = buffer_size; in virgl_create_so_target()
50 t->handle = handle; in virgl_create_so_target()
52 res->bind_history |= PIPE_BIND_STREAM_OUTPUT; in virgl_create_so_target()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
70 #define DEBUG_TYPE "arm-ldst-opt"
90 AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
97 /// Post- register allocation pass the combine load / store instructions to
127 /// A set of load/store MachineInstrs with same base register sorted by
170 unsigned Base, unsigned WordOffset,
174 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
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/third_party/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_cs.c11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
32 struct radeon_cmdbuf base; member
37 radv_null_cs(struct radeon_cmdbuf *base) in radv_null_cs() argument
39 return (struct radv_null_cs *)base; in radv_null_cs()
75 cs->ws = radv_null_winsys(ws); in radv_null_cs_create()
77 cs->base.buf = malloc(16384); in radv_null_cs_create()
78 cs->base.max_dw = 4096; in radv_null_cs_create()
79 if (!cs->base.buf) { in radv_null_cs_create()
84 return &cs->base; in radv_null_cs_create()
97 FREE(cs->base.buf); in radv_null_cs_destroy()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp1 //===-- LanaiMemAluCombiner.cpp - Pass to combine memory & ALU operations -===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // The Lanai ISA supports instructions where a load/store modifies the base
15 // ld [ %r6 -- ], %r12
19 // add %r6, -4, %r6
23 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "lanai-mem-alu-combiner"
44 "disable-lanai-mem-alu-combiner", llvm::cl::init(false),
147 // Check if the machine instruction has non-volatile memory operands of the type
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/third_party/mindspore/mindspore-src/source/mindspore/ccsrc/plugin/device/gpu/kernel/
Dgpu_kernel_factory.h2 * Copyright 2019-2022 Huawei Technologies Co., Ltd
8 * http://www.apache.org/licenses/LICENSE-2.0
86 #define KERNEL_NAME(kernel, cnt) MERGE(kernel, cnt)
87 #define MERGE(kernel, cnt) kernel##cnt macro
90 …static_assert(std::is_base_of<NativeGpuKernelMod, OPCLASS>::value, " must be base of NativeGpuKern…
95 …static_assert(std::is_base_of<NativeGpuKernelMod, OPCLASS>::value, " must be base of NativeGpuKern…
100 …static_assert(std::is_base_of<NativeGpuKernelMod, OPCLASS<T>>::value, " must be base of NativeGpuK…
105 …static_assert(std::is_base_of<NativeGpuKernelMod, OPCLASS<T>>::value, " must be base of NativeGpuK…
110 …static_assert(std::is_base_of<NativeGpuKernelMod, OPCLASS<T, S>>::value, " must be base of NativeG…
115 …static_assert(std::is_base_of<NativeGpuKernelMod, OPCLASS<T, S, G>>::value, " must be base of Nati…
/third_party/skia/third_party/externals/harfbuzz/src/
Dhb-ot-shape-complex-indic.cc31 #include "hb-ot-shape-complex-indic.hh"
32 #include "hb-ot-shape-complex-indic-machine.hh"
33 #include "hb-ot-shape-complex-vowel-constraints.hh"
34 #include "hb-ot-layout.hh"
43 * Indic configurations. Note that we do not want to keep every single script-specific
44 * behavior in these tables necessarily. This should mainly be used for per-script
67 BLWF_MODE_PRE_AND_POST, /* Below-forms feature applied to pre-base and post-base. */
68 BLWF_MODE_POST_ONLY /* Below-forms feature applied to post-base only. */
181 hb_ot_map_builder_t *map = &plan->map; in collect_features_indic()
184 map->add_gsub_pause (setup_syllables_indic); in collect_features_indic()
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/third_party/mesa3d/src/freedreno/computerator/
Dir3_asm.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
33 struct ir3_shader *shader = ir3_parse_asm(c, &kernel->info, in); in ir3_asm_assemble()
35 errx(-1, "assembler failed"); in ir3_asm_assemble()
36 struct ir3_shader_variant *v = shader->variants; in ir3_asm_assemble()
38 kernel->v = v; in ir3_asm_assemble()
39 kernel->bin = v->bin; in ir3_asm_assemble()
41 kernel->base.local_size[0] = v->local_size[0]; in ir3_asm_assemble()
42 kernel->base.local_size[1] = v->local_size[1]; in ir3_asm_assemble()
43 kernel->base.local_size[2] = v->local_size[2]; in ir3_asm_assemble()
44 kernel->base.num_bufs = kernel->info.num_bufs; in ir3_asm_assemble()
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/third_party/skia/third_party/externals/abseil-cpp/absl/container/
Dbtree_set.h7 // https://www.apache.org/licenses/LICENSE-2.0
15 // -----------------------------------------------------------------------------
17 // -----------------------------------------------------------------------------
19 // This header file defines B-tree sets: sorted associative containers of
25 // These B-tree types are similar to the corresponding types in the STL
27 // of those types. However, because they are implemented using B-trees, they
31 // red-black tree nodes, B-tree sets use more generic B-tree nodes able to hold
33 // B-tree sets perform better than their `std::set` counterparts, because
36 // However, these types should not be considered drop-in replacements for
78 using Base = typename btree_set::btree_set_container; variable
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/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_context.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
47 u_upload_destroy(fd5_ctx->border_color_uploader); in fd5_context_destroy()
48 pipe_resource_reference(&fd5_ctx->border_color_buf, NULL); in fd5_context_destroy()
52 fd_bo_del(fd5_ctx->vsc_size_mem); in fd5_context_destroy()
53 fd_bo_del(fd5_ctx->blit_mem); in fd5_context_destroy()
55 fd_context_cleanup_common_vbos(&fd5_ctx->base); in fd5_context_destroy()
71 pctx = &fd5_ctx->base.base; in fd5_context_create()
72 pctx->screen = pscreen; in fd5_context_create()
74 fd5_ctx->base.flags = flags; in fd5_context_create()
75 fd5_ctx->base.dev = fd_device_ref(screen->dev); in fd5_context_create()
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/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_cl.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
31 cl->base = rzalloc_size(job, 1); /* TODO: don't use rzalloc */ in vc4_init_cl()
32 cl->next = cl->base; in vc4_init_cl()
33 cl->size = 0; in vc4_init_cl()
34 cl->job = job; in vc4_init_cl()
42 if (offset + space <= cl->size) in cl_ensure_space()
45 uint32_t size = MAX2(cl->size + space, cl->size * 2); in cl_ensure_space()
47 cl->base = reralloc(ralloc_parent(cl->base), cl->base, uint8_t, size); in cl_ensure_space()
48 cl->size = size; in cl_ensure_space()
49 cl->next = cl->base + offset; in cl_ensure_space()
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/third_party/mesa3d/src/freedreno/drm/virtio/
Dvirtio_ringbuffer.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
39 sync_wait(fd_submit->out_fence_fd, -1); in retire_execute()
40 close(fd_submit->out_fence_fd); in retire_execute()
47 fd_submit_del(&fd_submit->base); in retire_cleanup()
54 struct virtio_pipe *virtio_pipe = to_virtio_pipe(fd_submit->base.pipe); in flush_submit_list()
55 struct fd_device *dev = virtio_pipe->base.dev; in flush_submit_list()
63 assert(submit->pipe == &virtio_pipe->base); in flush_submit_list()
64 nr_cmds += to_fd_ringbuffer_sp(submit->primary)->u.nr_cmds; in flush_submit_list()
68 * assuming the max amount that nr->bos will grow is by the in flush_submit_list()
69 * nr_cmds, and just over-allocate a bit. in flush_submit_list()
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/third_party/python/
D.travis.yml4 # To cache doc-building dependencies and C compiler output.
6 - pip
7 - ccache
8 - directories:
9 - $HOME/multissl
13 - OPENSSL=1.1.1f
14 - OPENSSL_DIR="$HOME/multissl/openssl/${OPENSSL}"
15 - PATH="${OPENSSL_DIR}/bin:$PATH"
16 - CFLAGS="-I${OPENSSL_DIR}/include"
17 - LDFLAGS="-L${OPENSSL_DIR}/lib"
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/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_context.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
45 u_upload_destroy(fd3_ctx->border_color_uploader); in fd3_context_destroy()
46 pipe_resource_reference(&fd3_ctx->border_color_buf, NULL); in fd3_context_destroy()
50 fd_bo_del(fd3_ctx->vs_pvt_mem); in fd3_context_destroy()
51 fd_bo_del(fd3_ctx->fs_pvt_mem); in fd3_context_destroy()
52 fd_bo_del(fd3_ctx->vsc_size_mem); in fd3_context_destroy()
54 fd_context_cleanup_common_vbos(&fd3_ctx->base); in fd3_context_destroy()
72 pctx = &fd3_ctx->base.base; in fd3_context_create()
73 pctx->screen = pscreen; in fd3_context_create()
75 fd3_ctx->base.flags = flags; in fd3_context_create()
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