Home
last modified time | relevance | path

Searched +full:mips +full:- +full:cpc (Results 1 – 25 of 43) sorted by relevance

12

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/
Dmti,mips-cpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Cluster Power Controller
10 Defines a location of the MIPS Cluster Power Controller registers.
13 - Paul Burton <paulburton@kernel.org>
17 const: mti,mips-cpc
22 used to map the MIPS CPC registers block.
26 - compatible
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/
Dmti,mips-cpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Cluster Power Controller
10 Defines a location of the MIPS Cluster Power Controller registers.
13 - Paul Burton <paulburton@kernel.org>
17 const: mti,mips-cpc
22 used to map the MIPS CPC registers block.
26 - compatible
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/
Dmips-cpc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h
17 /* The base address of the CPC registers */
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
22 * the CPC
26 * implemented per-platform.
31 * mips_cpc_probe - probe for a Cluster Power Controller
34 * a CPC is successfully detected, else -errno.
41 return -ENODEV; in mips_cpc_probe()
[all …]
Dmips-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
104 #include <asm/mips-cm.h>
105 #include <asm/mips-cpc.h>
106 #include <asm/mips-gic.h>
109 * mips_cps_numclusters - return the number of clusters present in the system
126 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
148 * GCR_CONFIG via the redirect region, since the CPC is always in mips_cps_cluster_config()
160 * mips_cps_numcores - return the number of cores present in a cluster
176 * mips_cps_numiocu - return the number of IOCUs present in a cluster
[all …]
Dpm-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
13 * enter or exit states requiring CM or CPC assistance in unison.
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
Ddsemul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
24 * mips_dsemul() - 'Emulate' an instruction from a branch delay slot
30 * Emulate or execute an arbitrary MIPS instruction within the context of
41 * do_dsemulret() - Return from a delay slot 'emulation' frame
47 * passed as the cpc parameter to mips_dsemul().
61 * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
78 * dsemul_thread_rollback() - Rollback from an 'emulation' frame
99 * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
103 * for delay slot 'emulation' book-keeping is freed. This is to be called
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/
Dmips-cpc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h
17 /* The base address of the CPC registers */
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
22 * the CPC
26 * implemented per-platform.
31 * mips_cpc_probe - probe for a Cluster Power Controller
34 * a CPC is successfully detected, else -errno.
41 return -ENODEV; in mips_cpc_probe()
[all …]
Dmips-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
105 #include <asm/mips-cm.h>
106 #include <asm/mips-cpc.h>
107 #include <asm/mips-gic.h>
110 * mips_cps_numclusters - return the number of clusters present in the system
123 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
145 * GCR_CONFIG via the redirect region, since the CPC is always in mips_cps_cluster_config()
157 * mips_cps_numcores - return the number of cores present in a cluster
174 * mips_cps_numiocu - return the number of IOCUs present in a cluster
[all …]
Dpm-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
13 * enter or exit states requiring CM or CPC assistance in unison.
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
Ddsemul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
24 * mips_dsemul() - 'Emulate' an instruction from a branch delay slot
30 * Emulate or execute an arbitrary MIPS instruction within the context of
41 * do_dsemulret() - Return from a delay slot 'emulation' frame
47 * passed as the cpc parameter to mips_dsemul().
61 * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
78 * dsemul_thread_rollback() - Rollback from an 'emulation' frame
99 * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
103 * for delay slot 'emulation' book-keeping is freed. This is to be called
[all …]
Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25 * __mips_cm_phys_base - retrieve the physical base address of the CM
37 * mips_cm_is64 - determine CM register width
42 * or vice-versa. This variable indicates the width of the memory accesses
46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
51 * mips_cm_error_report - Report CM cache errors
60 * mips_cm_probe - probe for a Coherence Manager
[all …]
/kernel/linux/linux-5.10/arch/mips/kernel/
Dmips-cpc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
13 #include <asm/mips-cps.h>
27 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc"); in mips_cpc_default_phys_base()
39 * mips_cpc_phys_base - retrieve the physical base address of the CPC
55 /* If the CPC is already enabled, leave it so */ in mips_cpc_phys_base()
65 /* Enable the CPC, mapped at the default address */ in mips_cpc_phys_base()
80 return -ENODEV; in mips_cpc_probe()
84 return -ENXIO; in mips_cpc_probe()
94 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_lock_other()
[all …]
Dpm-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
21 #include <asm/smp-cps.h>
25 * cps_nc_entry_fn - type of a generated non-coherent state entry function
27 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
29 * The code entering & exiting non-coherent states is generated at runtime
32 * core-specific code particularly for cache routines. If coupled_coherence
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS kernel.
6 extra-y := head.o vmlinux.lds
8 obj-y += branch.o cmpxchg.o elf.o entry.o genex.o idle.o irq.o \
14 obj-y += cpu-r3k-probe.o
16 obj-y += cpu-probe.o
20 CFLAGS_REMOVE_ftrace.o = -pg
21 CFLAGS_REMOVE_early_printk.o = -pg
22 CFLAGS_REMOVE_perf_event.o = -pg
23 CFLAGS_REMOVE_perf_event_mipsxx.o = -pg
[all …]
/kernel/linux/linux-6.6/arch/mips/kernel/
Dmips-cpc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
14 #include <asm/mips-cps.h>
28 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc"); in mips_cpc_default_phys_base()
40 * mips_cpc_phys_base - retrieve the physical base address of the CPC
56 /* If the CPC is already enabled, leave it so */ in mips_cpc_phys_base()
66 /* Enable the CPC, mapped at the default address */ in mips_cpc_phys_base()
81 return -ENODEV; in mips_cpc_probe()
85 return -ENXIO; in mips_cpc_probe()
95 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_lock_other()
[all …]
Dpm-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
21 #include <asm/smp-cps.h>
25 * cps_nc_entry_fn - type of a generated non-coherent state entry function
27 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
29 * The code entering & exiting non-coherent states is generated at runtime
32 * core-specific code particularly for cache routines. If coupled_coherence
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS kernel.
6 extra-y := vmlinux.lds
8 obj-y += head.o branch.o cmpxchg.o elf.o entry.o genex.o idle.o irq.o \
14 obj-y += cpu-r3k-probe.o
16 obj-y += cpu-probe.o
26 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
27 obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
28 obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
29 obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/img/
Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/img/
Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mips-boards/
Dmalta.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6 * Defines of the Malta board specific address-MAP, registers, etc.
13 #include <asm/mips-boards/msc01_pci.h>
16 /* Mips interrupt controller found in SOCit variations */
55 * CPC Specific definitions
71 * Malta RTC-device indirect register access.
/kernel/linux/linux-6.6/arch/mips/include/asm/mips-boards/
Dmalta.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6 * Defines of the Malta board specific address-MAP, registers, etc.
13 #include <asm/mips-boards/msc01_pci.h>
16 /* Mips interrupt controller found in SOCit variations */
55 * CPC Specific definitions
71 * Malta RTC-device indirect register access.
/kernel/linux/linux-6.6/arch/mips/boot/dts/ralink/
Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/staging/mt7621-dts/
Dmt7621.dtsi1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mediatek,mt7621-soc";
11 compatible = "mips,mips1004Kc";
15 compatible = "mips,mips1004Kc";
20 #address-cells = <0>;
21 #interrupt-cells = <1>;
22 interrupt-controller;
[all …]
/kernel/linux/linux-6.6/drivers/clocksource/
Dmips-gic-timer.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
17 #include <asm/mips-cps.h>
54 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
66 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
75 cd->event_handler(cd); in gic_compare_interrupt()
89 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
90 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
93 cd->rating = 350; in gic_clockevent_cpu_init()
[all …]
/kernel/linux/linux-5.10/drivers/clocksource/
Dmips-gic-timer.c6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 #define pr_fmt(fmt) "mips-gic-timer: " fmt
22 #include <asm/mips-cps.h>
59 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
71 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
80 cd->event_handler(cd); in gic_compare_interrupt()
94 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
95 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
98 cd->rating = 350; in gic_clockevent_cpu_init()
99 cd->irq = gic_timer_irq; in gic_clockevent_cpu_init()
[all …]

12