Home
last modified time | relevance | path

Searched +full:msi +full:- +full:base +full:- +full:vec (Results 1 – 25 of 60) sorted by relevance

123

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
/kernel/linux/linux-6.6/arch/powerpc/sysdev/xics/
Dics-native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/msi.h>
34 void __iomem *base; member
40 static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec) in ics_native_xive() argument
42 return in->base + 0x800 + ((vec - in->ibase) << 2); in ics_native_xive()
47 unsigned int vec = (unsigned int)irqd_to_hwirq(d); in ics_native_unmask_irq() local
52 pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec); in ics_native_unmask_irq()
54 if (vec < in->ibase || vec >= (in->ibase + in->icount)) in ics_native_unmask_irq()
57 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); in ics_native_unmask_irq()
58 out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY); in ics_native_unmask_irq()
[all …]
/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
43 .name = "PCH PCI MSI",
54 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
56 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
59 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
60 return -ENOSPC; in pch_msi_allocate_hwirq()
63 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Loongson PCH MSI support
9 #define pr_fmt(fmt) "pch-msi: " fmt
12 #include <linux/msi.h>
46 .name = "PCH PCI MSI",
57 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
59 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
62 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
63 return -ENOSPC; in pch_msi_allocate_hwirq()
66 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/loongson/
Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
[all …]
Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/
Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
[all …]
Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
[all …]
/kernel/linux/linux-6.6/drivers/crypto/cavium/nitrox/
Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
19 /* base entry for packet ring/port */
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
207 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
210 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
220 * nps_core_int_isr - interrupt handler for NITROX errors and
[all …]
/kernel/linux/linux-5.10/drivers/crypto/cavium/nitrox/
Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
14 * - NPS packet ring, AQMQ ring and ZQMQ ring
18 /* base entry for packet ring/port */
23 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
31 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
33 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
36 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
206 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
209 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
219 * nps_core_int_isr - interrupt handler for NITROX errors and
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4vf/
Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
78 * msi = 1: only consider MSI interrupts
82 * the PCI-E SR-IOV standard).
88 static int msi = MSI_DEFAULT; variable
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb4vf/
Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
78 * msi = 1: only consider MSI interrupts
82 * the PCI-E SR-IOV standard).
88 static int msi = MSI_DEFAULT; variable
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/4xx/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adding PCI-E MSI support for PPC4XX SoCs.
12 #include <linux/msi.h>
19 #include <asm/ppc-pci.h>
21 #include <asm/dcr-regs.h>
51 err = msi_bitmap_alloc(&msi_data->bitmap, msi_irqs, in ppc4xx_msi_init_allocator()
52 dev->dev.of_node); in ppc4xx_msi_init_allocator()
56 err = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
58 msi_bitmap_free(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
67 int int_no = -ENOMEM; in ppc4xx_setup_msi_irqs()
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-ismt.c65 #include <linux/dma-mapping.h>
70 #include <linux/io-64-nonatomic-lo-hi.h>
87 /* Hardware Descriptor Constants - Control Field */
96 /* Hardware Descriptor Constants - Status Field */
117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
174 struct ismt_desc *hw; /* descriptor virt base addr */
175 dma_addr_t io_rng_dma; /* descriptor HW base addr */
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
[all …]
/kernel/linux/linux-5.10/drivers/ntb/hw/amd/
Dntb_hw_amd.c8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
17 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
65 #define NTB_DESC "AMD(R) PCI-E Non-Transparent Bridge Driver"
78 if (idx < 0 || idx > ndev->mw_count) in ndev_mw_to_bar()
79 return -EINVAL; in ndev_mw_to_bar()
81 return ndev->dev_data->mw_idx << idx; in ndev_mw_to_bar()
87 return -EINVAL; in amd_ntb_mw_count()
89 return ntb_ndev(ntb)->mw_count; in amd_ntb_mw_count()
101 return -EINVAL; in amd_ntb_mw_get_align()
114 *size_max = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_mw_get_align()
[all …]
/kernel/linux/linux-6.6/drivers/ntb/hw/amd/
Dntb_hw_amd.c8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
17 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
65 #define NTB_DESC "AMD(R) PCI-E Non-Transparent Bridge Driver"
78 if (idx < 0 || idx > ndev->mw_count) in ndev_mw_to_bar()
79 return -EINVAL; in ndev_mw_to_bar()
81 return ndev->dev_data->mw_idx << idx; in ndev_mw_to_bar()
87 return -EINVAL; in amd_ntb_mw_count()
89 return ntb_ndev(ntb)->mw_count; in amd_ntb_mw_count()
101 return -EINVAL; in amd_ntb_mw_get_align()
114 *size_max = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_mw_get_align()
[all …]
/kernel/linux/linux-6.6/drivers/i2c/busses/
Di2c-ismt.c65 #include <linux/dma-mapping.h>
70 #include <linux/io-64-nonatomic-lo-hi.h>
87 /* Hardware Descriptor Constants - Control Field */
96 /* Hardware Descriptor Constants - Status Field */
117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
174 struct ismt_desc *hw; /* descriptor virt base addr */
175 dma_addr_t io_rng_dma; /* descriptor HW base addr */
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
[all …]
/kernel/linux/linux-5.10/arch/ia64/kernel/
Dirq_ia64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
54 /* default base addr of IPI table */
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
98 return -ENOSPC; in find_unassigned_irq()
[all …]
/kernel/linux/linux-6.6/arch/ia64/kernel/
Dirq_ia64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
54 /* default base addr of IPI table */
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
98 return -ENOSPC; in find_unassigned_irq()
[all …]
/kernel/linux/linux-6.6/drivers/ntb/hw/intel/
Dntb_hw_gen1.c9 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
19 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
66 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
74 #define bar0_off(base, bar) ((base) + ((bar) << 2)) argument
75 #define bar2_off(base, bar) bar0_off(base, (bar) - 2) argument
88 static int b2b_mw_idx = -1;
105 "XEON B2B USD BAR 2 64-bit address");
110 "XEON B2B USD BAR 4 64-bit address");
115 "XEON B2B USD split-BAR 4 32-bit address");
120 "XEON B2B USD split-BAR 5 32-bit address");
[all …]
/kernel/linux/linux-5.10/drivers/ntb/hw/intel/
Dntb_hw_gen1.c9 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
19 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
66 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
74 #define bar0_off(base, bar) ((base) + ((bar) << 2)) argument
75 #define bar2_off(base, bar) bar0_off(base, (bar) - 2) argument
88 static int b2b_mw_idx = -1;
105 "XEON B2B USD BAR 2 64-bit address");
110 "XEON B2B USD BAR 4 64-bit address");
115 "XEON B2B USD split-BAR 4 32-bit address");
120 "XEON B2B USD split-BAR 5 32-bit address");
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb3/
Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb3/
Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
[all …]
/kernel/linux/linux-6.6/arch/alpha/kernel/
Dsys_marvel.c1 // SPDX-License-Identifier: GPL-2.0
52 * -----+-----+--------+--- in io7_device_interrupt()
57 * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) in io7_device_interrupt()
58 * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) in io7_device_interrupt()
61 irq = ((vector & 0xffff) - 0x800) >> 4; in io7_device_interrupt()
81 "%s for nonexistent io7 -- vec %x, pid %d\n", in io7_get_irq_ctl()
87 irq -= 16; /* subtract legacy bias */ in io7_get_irq_ctl()
91 "%s for invalid irq -- pid %d adjusted irq %x\n", in io7_get_irq_ctl()
96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
97 if (irq >= 0x80) /* MSI */ in io7_get_irq_ctl()
[all …]

123