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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mux/
Dmux-consumer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mux/
Dmux-controller.txt4 A multiplexer (or mux) controller will have one, or several, consumer devices
5 that uses the mux controller. Thus, a mux controller can possibly control
7 multiplexer needed by each consumer, but a single mux controller can of course
10 A mux controller provides a number of states to its consumers, and the state
11 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
12 0-7 for an 8-way multiplexer, etc.
16 ---------
18 Mux controller consumers should specify a list of mux controllers that they
19 want to use with a property containing a 'mux-ctrl-list':
21 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
88 * @offset: if initialized to -1 it will be autocalculated, by specifying
121 * @offset: if initialized to -1 it will be autocalculated, by specifying
188 { .offset = -1 }, \
189 { .offset = -1 }, \
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
[all …]
/kernel/linux/linux-6.6/drivers/tty/
Dn_gsm.c1 // SPDX-License-Identifier: GPL-2.0
9 * tty -> DLCI fifo -> scheduler -> GSM MUX data queue ---o-> ldisc
10 * control message -> GSM MUX control queue --´
13 * ldisc -> gsm_queue() -o--> tty
14 * `-> gsm_control_response()
24 * Review the locking/move to refcounts more (mux now moved to an
29 * Do we need a 'which mux are you' ioctl to correlate mux and tty sets
95 * Semi-arbitrary buffer size limits. 0710 is normally run with 32-64 byte
101 /* SOF, ADDR, CTRL, LEN1, LEN2, ..., FCS, EOF */
106 * struct gsm_mux_net - network interface
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Doxnas,pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
9 pins, optional function, and optional mux related configuration.
12 - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
13 - oxsemi,sys-ctrl: a phandle to the system controller syscon node
15 Required properties for pin configuration sub-nodes:
16 - pins: List of pins to which the configuration applies.
18 Optional properties for pin configuration sub-nodes:
19 ----------------------------------------------------
20 - function: Mux function for the specified pins.
[all …]
/kernel/linux/linux-5.10/drivers/tty/
Dn_gsm.c1 // SPDX-License-Identifier: GPL-2.0
16 * Review the locking/move to refcounts more (mux now moved to an
21 * Do we need a 'which mux are you' ioctl to correlate mux and tty sets
71 * Semi-arbitrary buffer size limits. 0710 is normally run with 32-64 byte
76 /* SOF, ADDR, CTRL, LEN1, LEN2, ..., FCS, EOF */
81 * struct gsm_mux_net - network interface
97 struct list_head list; member
99 u8 ctrl; /* Control byte + flags */ member
120 * complexity right now these are only ever freed up when the mux is
123 * At the moment we don't free DLCI objects until the mux is torn down
[all …]
/kernel/linux/linux-6.6/include/net/caif/
Dcaif_layer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson AB 2010
10 #include <linux/list.h>
21 * caif_assert() - Assert function for CAIF.
36 * enum caif_ctrlcmd - CAIF Stack Control Signaling sent in layer.ctrlcmd().
50 * @CAIF_CTRLCMD_DEINIT_RSP: Called when de-initialization is
79 * enum caif_modemcmd - Modem Control Signaling, sent from CAIF Client
104 * enum caif_direction - CAIF Packet Direction.
115 * struct cflayer - CAIF Stack layer.
119 * @node: List node used when layer participate in a list.
[all …]
/kernel/linux/linux-5.10/include/net/caif/
Dcaif_layer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson AB 2010
10 #include <linux/list.h>
21 * caif_assert() - Assert function for CAIF.
36 * enum caif_ctrlcmd - CAIF Stack Control Signaling sent in layer.ctrlcmd().
50 * @CAIF_CTRLCMD_DEINIT_RSP: Called when de-initialization is
79 * enum caif_modemcmd - Modem Control Signaling, sent from CAIF Client
104 * enum caif_direction - CAIF Packet Direction.
115 * struct cflayer - CAIF Stack layer.
119 * @node: List node used when layer participate in a list.
[all …]
/kernel/linux/linux-6.6/drivers/net/wwan/iosm/
Diosm_ipc_mux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
8 /* At the begin of the runtime phase the IP MUX channel shall created. */
13 channel_id = ipc_imem_channel_alloc(ipc_mux->imem, ipc_mux->instance_id, in ipc_mux_channel_create()
17 dev_err(ipc_mux->dev, in ipc_mux_channel_create()
18 "allocation of the MUX channel id failed"); in ipc_mux_channel_create()
19 ipc_mux->state = MUX_S_ERROR; in ipc_mux_channel_create()
20 ipc_mux->event = MUX_E_NOT_APPLICABLE; in ipc_mux_channel_create()
24 /* Establish the MUX channel in blocking mode. */ in ipc_mux_channel_create()
25 ipc_mux->channel = ipc_imem_channel_open(ipc_mux->imem, channel_id, in ipc_mux_channel_create()
[all …]
Diosm_ipc_mux_codec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
12 /* Test the link power state and send a MUX command in blocking mode. */
16 struct iosm_mux *ipc_mux = ipc_imem->mux; in ipc_mux_tq_cmd_send()
19 skb_queue_tail(&ipc_mux->channel->ul_list, acb->skb); in ipc_mux_tq_cmd_send()
20 ipc_imem_ul_send(ipc_mux->imem); in ipc_mux_tq_cmd_send()
27 struct completion *completion = &ipc_mux->channel->ul_sem; in ipc_mux_acb_send()
28 int ret = ipc_task_queue_send_task(ipc_mux->imem, ipc_mux_tq_cmd_send, in ipc_mux_acb_send()
29 0, &ipc_mux->acb, in ipc_mux_acb_send()
30 sizeof(ipc_mux->acb), false); in ipc_mux_acb_send()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-mux-gpmux.txt1 General Purpose I2C Bus Mux
3 This binding describes an I2C bus multiplexer that uses a mux controller
4 from the mux subsystem to route the I2C signals.
6 .-----. .-----.
8 .------------. '-----' '-----'
10 | | .--------+--------'
11 | .------. | .------+ child bus A, on MUX value set to 0
12 | | I2C |-|--| Mux |
13 | '------' | '--+---+ child bus B, on MUX value set to 1
14 | .------. | | '----------+--------+--------.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/
Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
[all …]
/kernel/linux/linux-5.10/net/caif/
Dcfmuxl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2010
44 static void cfmuxl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl,
54 this->layer.receive = cfmuxl_receive; in cfmuxl_create()
55 this->layer.transmit = cfmuxl_transmit; in cfmuxl_create()
56 this->layer.ctrlcmd = cfmuxl_ctrlcmd; in cfmuxl_create()
57 INIT_LIST_HEAD(&this->srvl_list); in cfmuxl_create()
58 INIT_LIST_HEAD(&this->frml_list); in cfmuxl_create()
59 spin_lock_init(&this->transmit_lock); in cfmuxl_create()
60 spin_lock_init(&this->receive_lock); in cfmuxl_create()
[all …]
/kernel/linux/linux-6.6/net/caif/
Dcfmuxl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2010
44 static void cfmuxl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl,
54 this->layer.receive = cfmuxl_receive; in cfmuxl_create()
55 this->layer.transmit = cfmuxl_transmit; in cfmuxl_create()
56 this->layer.ctrlcmd = cfmuxl_ctrlcmd; in cfmuxl_create()
57 INIT_LIST_HEAD(&this->srvl_list); in cfmuxl_create()
58 INIT_LIST_HEAD(&this->frml_list); in cfmuxl_create()
59 spin_lock_init(&this->transmit_lock); in cfmuxl_create()
60 spin_lock_init(&this->receive_lock); in cfmuxl_create()
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
63 * @val: ctrl setting value
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
65 * @subname: (optional) additional ctrl setting name, e.g. rts, cts
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
95 * struct mvebu_mpp_mode - link ctrl and settings
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
63 * @val: ctrl setting value
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
65 * @subname: (optional) additional ctrl setting name, e.g. rts, cts
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
95 * struct mvebu_mpp_mode - link ctrl and settings
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 #include <dt-bindings/pinctrl/samsung.h>
31 #include "pinctrl-samsung.h"
36 /* list of all possible config options supported */
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
[all …]
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
77 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
108 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
110 * @pctl_offset: starting offset of the pin-bank registers.
111 * @pctl_res_idx: index of base address for pin-bank registers.
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/samsung/
Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
31 #include "pinctrl-samsung.h"
36 /* list of all possible config options supported */
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
[all …]
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
118 * @pctl_offset: starting offset of the pin-bank registers.
119 * @pctl_res_idx: index of base address for pin-bank registers.
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/actions/
Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
41 .mfpctl_reg = -1, \
42 .mfpctl_shift = -1, \
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/actions/
Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
41 .mfpctl_reg = -1, \
42 .mfpctl_shift = -1, \
[all …]
/kernel/linux/linux-6.6/drivers/comedi/drivers/
Dpcl818.c1 // SPDX-License-Identifier: GPL-2.0
6 * Description: Advantech PCL-818 cards, PCL-718
8 * Devices: [Advantech] PCL-818L (pcl818l), PCL-818H (pcl818h),
9 * PCL-818HD (pcl818hd), PCL-818HG (pcl818hg), PCL-818 (pcl818),
10 * PCL-718 (pcl718)
14 * Differences are only at maximal sample speed, range list and FIFO
18 * PCL-818HD and PCL-818HG support 1kword FIFO. Driver support this FIFO
37 * Options for PCL-818L:
38 * [0] - IO Base
39 * [1] - IRQ (0=disable, 2, 3, 4, 5, 6, 7)
[all …]
/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
Dpcl818.c1 // SPDX-License-Identifier: GPL-2.0
6 * Description: Advantech PCL-818 cards, PCL-718
8 * Devices: [Advantech] PCL-818L (pcl818l), PCL-818H (pcl818h),
9 * PCL-818HD (pcl818hd), PCL-818HG (pcl818hg), PCL-818 (pcl818),
10 * PCL-718 (pcl718)
14 * Differences are only at maximal sample speed, range list and FIFO
18 * PCL-818HD and PCL-818HG support 1kword FIFO. Driver support this FIFO
37 * Options for PCL-818L:
38 * [0] - IO Base
39 * [1] - IRQ (0=disable, 2, 3, 4, 5, 6, 7)
[all …]

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