| /kernel/linux/linux-5.10/drivers/mtd/nand/ |
| D | bbt.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
16 * nanddev_bbt_init() - Initialize the BBT (Bad Block Table)
17 * @nand: NAND device
19 * Initialize the in-memory BBT.
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
30 nand->bbt.cache = kcalloc(nwords, sizeof(*nand->bbt.cache), in nanddev_bbt_init()
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| /kernel/linux/linux-6.6/drivers/mtd/nand/ |
| D | bbt.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
16 * nanddev_bbt_init() - Initialize the BBT (Bad Block Table)
17 * @nand: NAND device
19 * Initialize the in-memory BBT.
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
28 nand->bbt.cache = bitmap_zalloc(nblocks * bits_per_block, GFP_KERNEL); in nanddev_bbt_init()
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | spinand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
15 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi-mem.h>
20 * Standard SPI NAND flash operations
144 * Standard SPI NAND flash commands
175 * struct spinand_id - SPI NAND id structure
192 * struct spinand_devid - SPI NAND device id structure
200 * read_id opcode + 1-byte address.
211 * struct manufacurer_ops - SPI NAND manufacturer specific operations
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| D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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| /kernel/linux/linux-6.6/include/linux/mtd/ |
| D | spinand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
15 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi-mem.h>
20 * Standard SPI NAND flash operations
144 * Standard SPI NAND flash commands
197 * struct spinand_id - SPI NAND id structure
214 * struct spinand_devid - SPI NAND device id structure
222 * read_id opcode + 1-byte address.
233 * struct manufacurer_ops - SPI NAND manufacturer specific operations
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| D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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| D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
97 * Enable generic NAND 'page erased' check. This check is only done when
98 * ecc.correct() returns -EBADMSG.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
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| D | flctl-nand.txt | 1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
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| D | flctl-nand.txt | 1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm63138.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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| D | armada-xp-98dx3236.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
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| D | spear13xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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| D | uniphier-ld4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
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| D | uniphier-sld8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/ |
| D | bcm63138.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
42 LP-DDR memories.
53 Used to configure the EBI (external bus interface) when the device-
70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
76 possible to tune the L2 cache performance up by setting the data,
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| /kernel/linux/linux-6.6/drivers/memory/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
74 possible to tune the L2 cache performance up by setting the data,
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
86 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
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| /kernel/linux/linux-5.10/drivers/mtd/nand/spi/ |
| D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
10 #define pr_fmt(fmt) "spi-nand: " fmt
21 #include <linux/spi/spi-mem.h>
26 spinand->scratchbuf); in spinand_read_reg_op()
29 ret = spi_mem_exec_op(spinand->spimem, &op); in spinand_read_reg_op()
33 *val = *spinand->scratchbuf; in spinand_read_reg_op()
40 spinand->scratchbuf); in spinand_write_reg_op()
42 *spinand->scratchbuf = val; in spinand_write_reg_op()
43 return spi_mem_exec_op(spinand->spimem, &op); in spinand_write_reg_op()
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/st/ |
| D | spear13xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/brcmnand/ |
| D | bcma_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
51 /* Offset into the NAND block and deal with the flash cache separately */ in brcmnand_bcma_read_reg()
57 val = bcma_cc_read32(sc->cc, offset); in brcmnand_bcma_read_reg()
70 /* Offset into the NAND block */ in brcmnand_bcma_write_reg()
80 bcma_cc_write32(sc->cc, offset, val); in brcmnand_bcma_write_reg()
93 /* Reset the cache address to ensure we are already accessing the in brcmnand_bcma_prepare_data_bus()
94 * beginning of a sub-page. in brcmnand_bcma_prepare_data_bus()
96 bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0); in brcmnand_bcma_prepare_data_bus()
101 struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev); in brcmnand_bcma_nand_probe()
104 soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL); in brcmnand_bcma_nand_probe()
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/socionext/ |
| D | uniphier-ld4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-ld4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mtk-snfi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/ |
| D | armada-xp-98dx3236.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
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