| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/ |
| D | nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/atmel/ |
| D | nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
24 #include <linux/jz4780-nemc.h>
28 #define DRV_NAME "ingenic-nand"
38 unsigned int bank;
39 void __iomem *base; member
47 unsigned int num_banks;
58 unsigned int reading: 1;
71 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section, in qi_lb60_ooblayout_ecc()
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc()
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
38 unsigned int bank;
39 void __iomem *base; member
47 unsigned int num_banks;
58 unsigned int reading: 1;
71 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section, in qi_lb60_ooblayout_ecc()
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc()
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | au1550nd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <asm/mach-au1x00/au1000.h>
15 #include <asm/mach-au1x00/au1550nd.h>
22 int cs;
23 void __iomem *base; member
32 * au_write_buf - write buffer to chip
33 * @this: NAND chip object
40 unsigned int len) in au_write_buf()
44 int i; in au_write_buf()
47 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
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| D | fsmc_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
37 #include <mtd/mtd-abi.h>
57 #define FSMC_NOR_REG(base, bank, reg) ((base) + \ argument
61 /* fsmc controller registers for NAND flash */
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
120 * struct fsmc_nand_data - structure for FSMC NAND device state
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| D | cs553x_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * This is a device driver for the NAND flash controller found on
11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
34 /* NAND Timing MSRs */
35 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
39 /* NAND BAR MSRs */
46 #define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
55 /* Registers within the NAND flash controller BAR -- memory mapped */
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| D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
128 int steps;
129 unsigned int rdy_timeout_ms;
130 unsigned int len;
136 * struct anand - Defines the NAND chip related information
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| D | gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Device driver for NAND flash that uses a memory mapped interface to
11 * read/write the NAND commands and data, and GPIO pins for control signals
12 * (the DT binding refers to this as "GPIO assisted NAND flash")
25 #include <linux/mtd/nand-gpio.h>
31 struct nand_controller base; member
52 * Make sure the GPIO state changes occur in-order with writes to NAND
54 * Needed on PXA due to bus-reordering within the SoC itself (see section on
61 if (gpiomtd->io_sync) { in gpio_nand_dosync()
64 * What's required is what's here - a read from a separate in gpio_nand_dosync()
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | au1550nd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
23 int cs;
24 void __iomem *base; member
33 * au_write_buf - write buffer to chip
34 * @this: NAND chip object
41 unsigned int len) in au_write_buf()
45 int i; in au_write_buf()
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
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| D | fsmc_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
29 #include <linux/mtd/nand-ecc-sw-hamming.h>
37 #include <mtd/mtd-abi.h>
57 #define FSMC_NOR_REG(base, bank, reg) ((base) + \ argument
61 /* fsmc controller registers for NAND flash */
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
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| D | nand_base.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
50 static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page, in nand_pairing_dist3_get_info()
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| D | cs553x_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * This is a device driver for the NAND flash controller found on
11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
33 /* NAND Timing MSRs */
34 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
35 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
38 /* NAND BAR MSRs */
45 #define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
54 /* Registers within the NAND flash controller BAR -- memory mapped */
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| D | gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Device driver for NAND flash that uses a memory mapped interface to
11 * read/write the NAND commands and data, and GPIO pins for control signals
12 * (the DT binding refers to this as "GPIO assisted NAND flash")
25 #include <linux/mtd/nand-gpio.h>
31 struct nand_controller base; member
52 * Make sure the GPIO state changes occur in-order with writes to NAND
54 * Needed on PXA due to bus-reordering within the SoC itself (see section on
61 if (gpiomtd->io_sync) { in gpio_nand_dosync()
64 * What's required is what's here - a read from a separate in gpio_nand_dosync()
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| D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
142 int steps;
143 unsigned int rdy_timeout_ms;
144 unsigned int len;
150 * struct anand - Defines the NAND chip related information
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| D | davinci_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
23 #include <linux/platform_data/mtd-davinci.h>
24 #include <linux/platform_data/mtd-davinci-aemif.h>
27 * This is a device driver for the NAND flash controller found on the
32 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
33 * available on chips like the DM355 and OMAP-L137 and needed with the
34 * more error-prone MLC NAND chips.
36 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | spinand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
15 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi-mem.h>
20 * Standard SPI NAND flash operations
144 * Standard SPI NAND flash commands
175 * struct spinand_id - SPI NAND id structure
182 int len;
192 * struct spinand_devid - SPI NAND device id structure
200 * read_id opcode + 1-byte address.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
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| /kernel/linux/linux-6.6/include/linux/mtd/ |
| D | spinand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
15 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi-mem.h>
20 * Standard SPI NAND flash operations
144 * Standard SPI NAND flash commands
197 * struct spinand_id - SPI NAND id structure
204 int len;
214 * struct spinand_devid - SPI NAND device id structure
222 * read_id opcode + 1-byte address.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/brcmnand/ |
| D | bcm63138_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 void __iomem *base; member
33 void __iomem *mmio = priv->base + BCM63138_NAND_INT_STATUS; in bcm63138_nand_intc_ack()
48 void __iomem *mmio = priv->base + BCM63138_NAND_INT_EN; in bcm63138_nand_intc_set()
59 static int bcm63138_nand_probe(struct platform_device *pdev) in bcm63138_nand_probe()
61 struct device *dev = &pdev->dev; in bcm63138_nand_probe()
67 return -ENOMEM; in bcm63138_nand_probe()
68 soc = &priv->soc; in bcm63138_nand_probe()
70 priv->base = devm_platform_ioremap_resource_byname(pdev, "nand-int-base"); in bcm63138_nand_probe()
71 if (IS_ERR(priv->base)) in bcm63138_nand_probe()
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| D | bcm6368_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright 2000-2010 Broadcom Corporation
12 * Copyright 2000-2010 Broadcom Corporation
28 void __iomem *base; member
54 void __iomem *mmio = priv->base + BCM6368_NAND_INT; in bcm6368_nand_intc_ack()
72 void __iomem *mmio = priv->base + BCM6368_NAND_INT; in bcm6368_nand_intc_set()
86 static int bcm6368_nand_probe(struct platform_device *pdev) in bcm6368_nand_probe()
88 struct device *dev = &pdev->dev; in bcm6368_nand_probe()
94 return -ENOMEM; in bcm6368_nand_probe()
95 soc = &priv->soc; in bcm6368_nand_probe()
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| /kernel/linux/linux-5.10/arch/mips/netlogic/xlr/ |
| D | platform-flash.c | 43 * Default NAND partition layout
72 .name = "physmap-flash",
81 * Use "gen_nand" driver for NAND flash
85 * struct for now, since we currently have only one NAND chip per board.
88 int cs;
94 static void xlr_nand_ctrl(struct nand_chip *chip, int cmd, in xlr_nand_ctrl()
95 unsigned int ctrl) in xlr_nand_ctrl()
125 .id = -1,
135 * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
143 uint64_t flash_map_base, int cs, struct resource *res) in setup_flash_resource()
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/brcmnand/ |
| D | bcm63138_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 void __iomem *base; member
33 void __iomem *mmio = priv->base + BCM63138_NAND_INT_STATUS; in bcm63138_nand_intc_ack()
48 void __iomem *mmio = priv->base + BCM63138_NAND_INT_EN; in bcm63138_nand_intc_set()
59 static int bcm63138_nand_probe(struct platform_device *pdev) in bcm63138_nand_probe()
61 struct device *dev = &pdev->dev; in bcm63138_nand_probe()
68 return -ENOMEM; in bcm63138_nand_probe()
69 soc = &priv->soc; in bcm63138_nand_probe()
71 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-int-base"); in bcm63138_nand_probe()
72 priv->base = devm_ioremap_resource(dev, res); in bcm63138_nand_probe()
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| D | bcm6368_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright 2000-2010 Broadcom Corporation
12 * Copyright 2000-2010 Broadcom Corporation
28 void __iomem *base; member
54 void __iomem *mmio = priv->base + BCM6368_NAND_INT; in bcm6368_nand_intc_ack()
72 void __iomem *mmio = priv->base + BCM6368_NAND_INT; in bcm6368_nand_intc_set()
86 static int bcm6368_nand_probe(struct platform_device *pdev) in bcm6368_nand_probe()
88 struct device *dev = &pdev->dev; in bcm6368_nand_probe()
95 return -ENOMEM; in bcm6368_nand_probe()
96 soc = &priv->soc; in bcm6368_nand_probe()
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