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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
[all …]
Damlogic,meson-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
10 - $ref: nand-controller.yaml
13 - liang.yang@amlogic.com
18 - amlogic,meson-gxl-nfc
19 - amlogic,meson-axg-nfc
24 reg-names:
[all …]
Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments GPMC NAND Flash controller.
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
14 GPMC NAND controller/Flash is represented as a child of the
20 - enum:
21 - ti,am64-nand
[all …]
Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
[all …]
Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
19 {size} bytes for a particular raw NAND chip.
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
[all …]
Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller
10 - $ref: nand-controller.yaml
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
19 - allwinner,sun4i-a10-nand
20 - allwinner,sun8i-a23-nand-controller
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
[all …]
Dmarvell-nand.txt1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
[all …]
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
[all …]
Dgpmc-nand.txt3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
18 NAND I/O space
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
[all …]
Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller Device Tree Bindings
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/
Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
[all …]
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/atmel/
Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dpm9g45.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
39 nand {
40 pinctrl_nand_rb: nand-rb-0 {
47 pinctrl_board_mmc: mmc0-board {
56 compatible = "atmel,tcb-timer";
[all …]
Dat91-linea.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
22 clock-frequency = <32768>;
26 clock-frequency = <12000000>;
31 compatible = "atmel,tcb-timer";
36 compatible = "atmel,tcb-timer";
52 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
53 pinctrl-names = "default";
61 nand: nand@3 { label
63 atmel,rb = <0>;
[all …]
Dge863-pro3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
14 clock-frequency = <6000000>;
22 compatible = "atmel,tcb-timer";
27 compatible = "atmel,tcb-timer";
40 nand_controller: nand-controller {
42 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
43 pinctrl-names = "default";
45 nand@3 {
47 rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dpm9g45.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
39 nand {
40 pinctrl_nand_rb: nand-rb-0 {
47 pinctrl_board_mmc: mmc0-board {
56 compatible = "atmel,tcb-timer";
[all …]
Dat91-linea.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
22 clock-frequency = <32768>;
26 clock-frequency = <12000000>;
31 compatible = "atmel,tcb-timer";
36 compatible = "atmel,tcb-timer";
52 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
53 pinctrl-names = "default";
61 nand: nand@3 { label
63 atmel,rb = <0>;
[all …]
Dge863-pro3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
14 clock-frequency = <6000000>;
22 compatible = "atmel,tcb-timer";
27 compatible = "atmel,tcb-timer";
40 nand_controller: nand-controller {
42 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
43 pinctrl-names = "default";
45 nand@3 {
47 rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
[all …]
Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
18 stdout-path = "serial0:115200n8";
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pf_pins>;
36 nand@0 {
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
[all …]
Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/
Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
18 stdout-path = "serial0:115200n8";
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pf_pins>;
36 nand@0 {
[all …]

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