| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | xlnx,xps-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
20 clock-names:
29 '#pwm-cells': true
31 xlnx,count-width:
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| D | nvidia,tegra-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
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| D | arm,sp804.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
16 independently for each timer.
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
27 - arm,sp804
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| D | nvidia,tegra186-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 timer
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
14 counter. Each NV timer selects its timing reference signal from the 1 MHz
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
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| D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
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| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | apb_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 * The timer information, such as frequency and addresses, is provided to the
13 * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
15 * Unlike HPET, there is no master counter, therefore one of the timers are
17 * - timer 0 - NR_CPUs for per cpu timer
18 * - one timer for clocksource
19 * - one timer for watchdog driver.
20 * It is also worth notice that APB timer does not support true one-shot mode,
21 * free-running mode will be used here to emulate one-shot mode.
22 * APB timer can also be used as broadcast timer along with per cpu local APIC
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
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| D | arm,sp804.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
16 independently for each timer.
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
27 - const: arm,sp804
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| /kernel/linux/linux-5.10/Documentation/virt/kvm/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
20 One of the most complicated parts of the X86 platform, and specifically,
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
55 available, but not all modes are available to all timers, as only timer 2
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| /kernel/linux/linux-6.6/Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
20 One of the most complicated parts of the X86 platform, and specifically,
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
55 available, but not all modes are available to all timers, as only timer 2
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/microchip/ |
| D | atmel,at91rm9200-tcb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Timer Counter Block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
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| /kernel/linux/linux-5.10/Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
38 entity which appears to be fetching instructions that belong to one sequence
42 First, if the whole processor can only follow one sequence of instructions (one
46 Second, if the processor is multi-core, each core in it is able to follow at
47 least one program at a time. The cores need not be entirely independent of each
49 work physically in parallel with each other, so if each of them executes only
50 one program, those programs run mostly independently of each other at the same
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| /kernel/linux/linux-6.6/arch/arm/mach-at91/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
34 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
45 Select this if you are using one of Microchip's SAMA5D3 family SoC.
59 Select this if you are using one of Microchip's SAMA5D4 family SoC.
70 Select this if you are using one of Microchip's SAMA7G5 family SoC.
110 Select this if you are using one of those Microchip SoC:
147 bool "Periodic Interval Timer (PIT) support"
153 Timer. It has a relatively low resolution and the TC Block clocksource
157 bool "Timer Counter Blocks (TCB) support"
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | intel_scu_watchdog.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * - AF82MP20 PCH
7 * Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
35 #include <asm/intel-mid.h>
48 "Watchdog timer margin"
56 "Default Watchdog timer setting"
71 "the watchdog timer will be refreshed for one more interval"
73 "watchdog timer will reset the system."
76 /* there is only one device in the system now; this can be made into
77 * an array in the future if we have more than one device */
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 bool "Watchdog Timer Support"
10 If you say Y here (and to one of the following options) and create a
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
34 tristate "WatchDog Timer Driver Core"
36 Say Y here if you want to use the new watchdog timer driver core.
37 This driver provides a framework for all watchdog timer drivers
45 to stop the timer if the process managing it closes the file
51 bool "Update boot-enabled watchdog until userspace takes over"
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| /kernel/linux/linux-5.10/arch/powerpc/oprofile/cell/ |
| D | spu_profiler.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <asm/cell-pmu.h>
28 * per system as a result of the user starting/stopping oprofile. Hence, only
29 * one CPU per user at a time will be changing the value of spu_prof_running.
83 * the two 64-bit buffer entries that make up the in spu_pc_extract()
84 * 128-bit trace_buffer entry. Process two 64-bit values in spu_pc_extract()
92 for (spu = SPUS_PER_TB_ENTRY-1; spu >= 0; spu--) { in spu_pc_extract()
133 static enum hrtimer_restart profile_spus(struct hrtimer *timer) in profile_spus() argument
147 /* There should only be one kernel thread at a time processing in profile_spus()
150 * started to process the samples. Make sure only one kernel in profile_spus()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/ |
| D | marvell,cn10624-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
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| /kernel/linux/linux-5.10/arch/parisc/kernel/ |
| D | time.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * 1994-07-02 Alan Modra
11 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
43 static unsigned long clocktick __ro_after_init; /* timer cycles per tick */
46 * We keep time on PA-RISC Linux by using the Interval Timer which is
47 * a pair of registers; one is read-only and one is write-only; both
48 * accessed through CR16. The read-only register is 32 or 64 bits wide,
49 * and increments by 1 every CPU clock tick. The architecture only
51 * rate of 1. The write-only register is 32-bits wide. When the lowest
52 * 32 bits of the read-only register compare equal to the write-only
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| /kernel/linux/linux-6.6/arch/parisc/kernel/ |
| D | time.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * 1994-07-02 Alan Modra
11 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
45 static unsigned long clocktick __ro_after_init; /* timer cycles per tick */
48 * We keep time on PA-RISC Linux by using the Interval Timer which is
49 * a pair of registers; one is read-only and one is write-only; both
50 * accessed through CR16. The read-only register is 32 or 64 bits wide,
51 * and increments by 1 every CPU clock tick. The architecture only
53 * rate of 1. The write-only register is 32-bits wide. When the lowest
54 * 32 bits of the read-only register compare equal to the write-only
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| /kernel/linux/linux-5.10/arch/arm/mach-at91/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
33 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
44 Select this if you are using one of Microchip's SAMA5D3 family SoC.
58 Select this if you are using one of Microchip's SAMA5D4 family SoC.
90 Select this if you are using one of those Microchip SoC:
128 bool "Periodic Interval Timer (PIT) support"
134 Timer. It has a relatively low resolution and the TC Block clocksource
138 bool "Timer Counter Blocks (TCB) support"
144 On platforms with 16-bit counters, two timer channels are combined
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| /kernel/linux/linux-6.6/Documentation/arch/mips/ |
| D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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| /kernel/linux/linux-5.10/Documentation/mips/ |
| D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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| /kernel/linux/linux-6.6/include/soc/at91/ |
| D | atmel_tcb.h | 2 * Timer/Counter Unit (TC) registers.
17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
38 * @counter_width: size in bits of a timer counter register
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
40 * @has_qdec: boolean indicating if a timer counter has a quadrature
50 * struct atmel_tc - information about a Timer/Counter Block
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| /kernel/linux/linux-5.10/include/soc/at91/ |
| D | atmel_tcb.h | 2 * Timer/Counter Unit (TC) registers.
17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
38 * @counter_width: size in bits of a timer counter register
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
40 * @has_qdec: boolean indicating if a timer counter has a quadrature
50 * struct atmel_tc - information about a Timer/Counter Block
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | timer-cs5535.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #define DRV_NAME "cs5535-clockevt"
26 * We are using the 32.768kHz input clock - it's the only one that has the
53 * as clock event sources - not as good as a HPET or APIC, but certainly
55 * a simplified one designed specifically to act as a clock event source.
59 static void disable_timer(struct cs5535_mfgpt_timer *timer) in disable_timer() argument
62 cs5535_mfgpt_write(timer, MFGPT_REG_SETUP, in disable_timer()
67 static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta) in start_timer() argument
69 cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta); in start_timer()
70 cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0); in start_timer()
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