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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
[all …]
Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
[all …]
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
[all …]
Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
[all …]
Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
56 -----------------------------------
61 5 pex1 PCIe 1
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
56 -----------------------------------
61 5 pex1 PCIe 1
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/cadence/
Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
58 (GENMASK(7, 5) << ((b) * 8))
60 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
67 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
108 (((aperture) - 2) << ((bar) * 8))
129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
132 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
134 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/cadence/
Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
67 (GENMASK(7, 5) << ((b) * 8))
69 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
117 (((aperture) - 2) << ((bar) * 8))
144 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
147 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 bool "Marvell EBU PCIe controller"
15 tristate "Aardvark PCIe controller"
21 Add support for Aardvark 64bit PCIe Host Controller. This
26 bool "NWL PCIe Core"
31 NWL PCIe controller. The controller can act as Root Port
41 bool "NVIDIA Tegra PCIe controller"
46 Say Y here if you want support for the PCIe host controller found
50 bool "Renesas R-Car Gen2 Internal PCI controller"
54 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/
Dpcie-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
/kernel/linux/linux-6.6/Documentation/admin-guide/perf/
Dhisi-pcie-pmu.rst2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
38 ------------------------------------------
40 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency/
41 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt/
42 $# perf stat -g -e hisi_pcie0_core0/rx_mwr_latency/ -e hisi_pcie0_core0/rx_mwr_cnt/
[all …]
/kernel/linux/linux-5.10/drivers/phy/broadcom/
Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
56 * @base: base register of PCIe SS
60 * @phys: array of PCIe PHYs
72 * PCIe PIPEMUX lookup table
75 * The array element represents a bitmap where a set bit means the PCIe
[all …]
/kernel/linux/linux-6.6/drivers/phy/broadcom/
Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
56 * @base: base register of PCIe SS
60 * @phys: array of PCIe PHYs
72 * PCIe PIPEMUX lookup table
75 * The array element represents a bitmap where a set bit means the PCIe
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mv78xx0/
Dmv78xx0.h19 * c0000000 PCIe Memory space
20 * f0800000 PCIe #0 I/O space
21 * f0900000 PCIe #1 I/O space
22 * f0a00000 PCIe #2 I/O space
23 * f0b00000 PCIe #3 I/O space
24 * f0c00000 PCIe #4 I/O space
25 * f0d00000 PCIe #5 I/O space
26 * f0e00000 PCIe #6 I/O space
27 * f0f00000 PCIe #7 I/O space
28 * f1000000 on-chip peripheral registers
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
84 #define REQ_NOT_ENTR_L1 BIT(5)
89 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
161 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
178 #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-mv78xx0/
Dmv78xx0.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * c0000000 PCIe Memory space
17 * f0800000 PCIe #0 I/O space
18 * f0900000 PCIe #1 I/O space
19 * f0a00000 PCIe #2 I/O space
20 * f0b00000 PCIe #3 I/O space
21 * f0c00000 PCIe #4 I/O space
22 * f0d00000 PCIe #5 I/O space
23 * f0e00000 PCIe #6 I/O space
24 * f0f00000 PCIe #7 I/O space
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/
Dpcie-mobiveil.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * PCIe host controller driver for Mobiveil PCIe Host controller
58 #define PAB_INTP_INTA BIT(5)
101 #define PAB_INTX_START 5
148 int (*interrupt_init)(struct mobiveil_pcie *pcie);
163 int (*link_up)(struct mobiveil_pcie *pcie);
170 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
179 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
180 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
181 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/mobiveil/
Dpcie-mobiveil.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * PCIe host controller driver for Mobiveil PCIe Host controller
58 #define PAB_INTP_INTA BIT(5)
101 #define PAB_INTX_START 5
148 int (*interrupt_init)(struct mobiveil_pcie *pcie);
163 int (*link_up)(struct mobiveil_pcie *pcie);
170 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
179 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
180 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
181 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
[all …]
/kernel/linux/linux-6.6/drivers/pci/hotplug/
Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
26 #include "../pcie/portdrv.h"
36 pci_dbg(ctrl->pcie->port, format, ## arg)
38 pci_err(ctrl->pcie->port, format, ## arg)
40 pci_info(ctrl->pcie->port, format, ## arg)
42 pci_warn(ctrl->pcie->port, format, ## arg)
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
[all …]
/kernel/linux/linux-5.10/drivers/pci/hotplug/
Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
26 #include "../pcie/portdrv.h"
36 pci_dbg(ctrl->pcie->port, format, ## arg)
38 pci_err(ctrl->pcie->port, format, ## arg)
40 pci_info(ctrl->pcie->port, format, ## arg)
42 pci_warn(ctrl->pcie->port, format, ## arg)
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
[all …]

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