| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
[all …]
|
| D | hisilicon,phy-hi3670-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin970 PCIe PHY
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
13 Bindings for PCIe PHY on HiSilicon Kirin 970.
17 const: hisilicon,hi970-pcie-phy
19 "#phy-cells":
24 description: PHY Control registers
[all …]
|
| D | brcm,cygnus-pcie-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Cygnus PCIe PHY
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
15 pattern: "^pcie[-|_]phy(@.*)?$"
19 - const: brcm,cygnus-pcie-phy
24 Base address and length of the PCIe PHY block
[all …]
|
| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
[all …]
|
| D | socionext,uniphier-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
[all …]
|
| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
[all …]
|
| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include "pcie-cadence.h"
11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
35 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
8 #include "pcie-cadence.h"
10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
34 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
46 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
6 - #address-cells: must be 1
7 - #size-cells: must be 0
9 Each PCIe PHY should be represented by a child node
12 - reg: the PHY ID
13 0 - PCIe RC 0
14 1 - PCIe RC 1
15 - #phy-cells: must be 0
[all …]
|
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
[all …]
|
| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
[all …]
|
| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
25 #include "pcie-designware.h"
33 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
61 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
71 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
[all …]
|
| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
14 #include <linux/phy/phy.h>
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
70 struct phy *phy; member
84 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
89 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
[all …]
|
| D | pcie-kirin.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Kirin Phone SoCs
22 #include <linux/phy/phy.h>
29 #include "pcie-designware.h"
31 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
33 /* PCIe ELBI registers */
60 * in-board Ethernet adapter and the other two connected to M.2 and mini
77 struct phy *phy; member
83 /* Per-slot PERST# */
88 /* Per-slot clkreq */
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
26 #include "pcie-designware.h"
34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
62 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
72 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
79 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
|
| D | pci-keystone.txt | 1 TI Keystone PCIe interface
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
[all …]
|
| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pcie-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
28 #include <linux/phy/phy.h>
35 /* MediaTek-specific configuration registers */
40 /* Host-PCI bridge registers */
48 /* PCIe RC control registers */
67 * struct mt7621_pcie_port - PCIe port information
70 * @pcie: pointer to PCIe host info
72 * @phy: pointer to PHY control block
[all …]
|
| D | pcie-iproc-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/phy/phy.h>
19 #include "pcie-iproc.h"
23 .compatible = "brcm,iproc-pcie",
26 .compatible = "brcm,iproc-pcie-paxb-v2",
29 .compatible = "brcm,iproc-pcie-paxc",
32 .compatible = "brcm,iproc-pcie-paxc-v2",
41 struct device *dev = &pdev->dev; in iproc_pltfm_pcie_probe()
42 struct iproc_pcie *pcie; in iproc_pltfm_pcie_probe() local
43 struct device_node *np = dev->of_node; in iproc_pltfm_pcie_probe()
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/broadcom/ |
| D | phy-bcm-cygnus-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25 * @core: pointer to the Cygnus PCIe PHY core control
26 * @id: internal ID to identify the Cygnus PCIe PHY
27 * @phy: pointer to the kernel PHY device
32 struct phy *phy; member
36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
40 * @phys: pointer to Cygnus PHY device
49 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable) in cygnus_pcie_power_config() argument
[all …]
|
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
[all …]
|
| D | phy-bcm-cygnus-pcie.c | 18 #include <linux/phy/phy.h>
34 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
35 * @core: pointer to the Cygnus PCIe PHY core control
36 * @id: internal ID to identify the Cygnus PCIe PHY
37 * @phy: pointer to the kernel PHY device
42 struct phy *phy; member
46 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
50 * @phys: pointer to Cygnus PHY device
59 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable) in cygnus_pcie_power_config() argument
61 struct cygnus_pcie_phy_core *core = phy->core; in cygnus_pcie_power_config()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-iproc-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/phy/phy.h>
20 #include "pcie-iproc.h"
24 .compatible = "brcm,iproc-pcie",
27 .compatible = "brcm,iproc-pcie-paxb-v2",
30 .compatible = "brcm,iproc-pcie-paxc",
33 .compatible = "brcm,iproc-pcie-paxc-v2",
42 struct device *dev = &pdev->dev; in iproc_pcie_pltfm_probe()
43 struct iproc_pcie *pcie; in iproc_pcie_pltfm_probe() local
44 struct device_node *np = dev->of_node; in iproc_pcie_pltfm_probe()
[all …]
|