| /kernel/linux/linux-5.10/drivers/staging/vc04_services/vchiq-mmal/ |
| D | mmal-msg-format.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include "mmal-msg-common.h"
25 u32 bits_per_sample; /* Bits per sample */
37 * FourCC specifying the color space of the video stream. See the
38 * MmalColorSpace "pre-defined color spaces" for some examples.
54 /* Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
59 * stream.
63 * stream.
68 * elementary stream
71 u32 bitrate; /* Bitrate in bits per second */
[all …]
|
| /kernel/linux/linux-6.6/drivers/staging/vc04_services/vchiq-mmal/ |
| D | mmal-msg-format.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include "mmal-msg-common.h"
27 u32 bits_per_sample; /* Bits per sample */
39 * FourCC specifying the color space of the video stream. See the
40 * MmalColorSpace "pre-defined color spaces" for some examples.
56 /* Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
61 * stream.
65 * stream.
70 * elementary stream
73 u32 bitrate; /* Bitrate in bits per second */
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-compressed.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
12 .. flat-table:: Compressed Image Formats
13 :header-rows: 1
14 :stub-columns: 0
17 * - Identifier
18 - Code
19 - Details
20 * .. _V4L2-PIX-FMT-JPEG:
22 - ``V4L2_PIX_FMT_JPEG``
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
101 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
141 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
101 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
141 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/ |
| D | ia_css_stream_public.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
36 IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */
37 IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */
38 IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */
51 stream */
66 enum atomisp_input_format format; /** Format of input stream. This data
69 int linked_isys_stream_id; /** default value is -1, other value means
81 enum atomisp_input_format format; /** Format of input stream. This data
87 /* Input stream description. This describes how input will flow into the
116 unsigned int pixels_per_clock; /** Number of pixels per clock, which can be
[all …]
|
| /kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/ |
| D | ia_css_stream_public.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
36 IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */
37 IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */
38 IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */
51 stream */
66 enum atomisp_input_format format; /** Format of input stream. This data
69 int linked_isys_stream_id; /** default value is -1, other value means
81 enum atomisp_input_format format; /** Format of input stream. This data
87 /* Input stream description. This describes how input will flow into the
114 unsigned int pixels_per_clock; /** Number of pixels per clock, which can be
[all …]
|
| /kernel/linux/linux-6.6/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-compressed.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
18 .. flat-table:: Compressed Image Formats
19 :header-rows: 1
20 :stub-columns: 0
23 * - Identifier
24 - Code
25 - Details
26 * .. _V4L2-PIX-FMT-JPEG:
28 - ``V4L2_PIX_FMT_JPEG``
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | frontend.json | 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
25 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
83 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
136 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop…
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswell/ |
| D | frontend.json | 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
25 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
83 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
136 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop…
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | frontend.json | 18 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
36 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
39 …mber of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
46 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
50 …ps are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
57 …"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Inst…
60 …"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB)…
67 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
71 …"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer…
79 …tion": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | frontend.json | 18 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
36 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
39 …mber of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
46 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
50 …ps are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
57 …"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Inst…
60 …"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB)…
67 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
71 …"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer…
79 …tion": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | frontend.json | 13 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
34 …mber of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
40 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
44 …ps are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
50 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
55 …"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB)…
61 …"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Inst…
65 …"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer…
71 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
76 …mber of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while…
[all …]
|
| /kernel/linux/linux-5.10/sound/usb/line6/ |
| D | pcm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2010 Markus Grabner (grabner@icg.tugraz.at)
20 number of USB frames per URB
21 The Line 6 Windows driver always transmits two frames per packet, but
23 with only one frame per packet.
37 #define get_substream(line6pcm, stream) \ argument
38 (line6pcm->pcm->streams[stream].substream)
49 capture and playback stream, which must be shared between these
54 or capture stream. Both can contain the bit flag corresponding to
60 the running flag indicates whether the stream is running.
[all …]
|
| /kernel/linux/linux-6.6/sound/usb/line6/ |
| D | pcm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2010 Markus Grabner (grabner@icg.tugraz.at)
20 number of USB frames per URB
21 The Line 6 Windows driver always transmits two frames per packet, but
23 with only one frame per packet.
37 #define get_substream(line6pcm, stream) \ argument
38 (line6pcm->pcm->streams[stream].substream)
49 capture and playback stream, which must be shared between these
54 or capture stream. Both can contain the bit flag corresponding to
60 the running flag indicates whether the stream is running.
[all …]
|
| /kernel/linux/linux-5.10/sound/firewire/dice/ |
| D | dice-interface.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * block read transactions with at least quadlet-aligned offset and length.
12 * Writes are not allowed except where noted; quadlet-sized registers must be
15 * All values are in big endian. The DICE firmware runs on a little-endian CPU
16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
32 * size values are measured in quadlets. Read-only.
50 * Stores the full 64-bit address (node ID and offset in the node's address
60 * A bitmask with asynchronous events; read-only. When any event(s) happen,
74 /* Other bits may be used for device-specific events. */
[all …]
|
| /kernel/linux/linux-6.6/sound/firewire/dice/ |
| D | dice-interface.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * block read transactions with at least quadlet-aligned offset and length.
12 * Writes are not allowed except where noted; quadlet-sized registers must be
15 * All values are in big endian. The DICE firmware runs on a little-endian CPU
16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
32 * size values are measured in quadlets. Read-only.
50 * Stores the full 64-bit address (node ID and offset in the node's address
60 * A bitmask with asynchronous events; read-only. When any event(s) happen,
74 /* Other bits may be used for device-specific events. */
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | frontend.json | 36 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
45 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
55 …"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Inst…
64 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
75 …tion": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while…
85 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
95 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
138 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
155 …"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pip…
188 …-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be de…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | frontend.json | 45 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
54 …"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Inst…
76 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
87 …-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be de…
93 …"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend…
102 …"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocatio…
112 …"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocatio…
122 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
126 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes…
132 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
|
| D | cdns,csi2rx.txt | 1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
|