Searched +full:phy +full:- +full:output +full:- +full:reference +full:- +full:clock (Results 1 – 25 of 257) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
7 phandle while referencing this phy. Should be "2". The 1st cell
8 corresponds to the phy type (should be one of the types specified in
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
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| D | phy-rockchip-inno-hdmi.txt | 1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
12 based refeference PLL clock input.
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| D | samsung,ufs-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY Device Tree Bindings
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
23 reg-names:
25 - const: phy-pma
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
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| D | nxp,tja11xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP TJA11xx PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 "^ethernet-phy@[0-9a-f]+$":
24 Some packages have multiple PHYs. Secondary PHY should be defines as
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| D | rockchip-dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
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| D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
28 power-domains:
34 Three input clocks referring to left input reference clock, refclk and right input reference
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| D | phy-rockchip-inno-hdmi.txt | 1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
12 based refeference PLL clock input.
[all …]
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| D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
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| D | mediatek,hdmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
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| D | mediatek,dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
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| D | samsung,ufs-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
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| D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | rockchip-dwmac.txt | 6 - compatible: should be "rockchip,<name>-gamc"
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
[all …]
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| D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
6 channel output.
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
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| D | mediatek,hdmi.txt | 8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
16 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17 - phy-names: must contain "hdmi"
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | nuvoton-common-npcm7xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
12 /* external reference clock */
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <25000000>;
17 clock-output-names = "refclk";
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
21 * This clock looks something like this
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
21 * This clock looks something like this
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-mediatek.c | 1 // SPDX-License-Identifier: GPL-2.0
94 /* clock ids to be requested */
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
118 /* select phy interface in top control domain */ in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
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