| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
[all …]
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| D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include "aptina-pll.h"
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
35 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
36 dev_err(dev, "pll: invalid pixel clock frequency.\n"); in aptina_pll_calculate()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | aptina,mt9p031.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
[all …]
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| D | imx258.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
12 description: |-
13 IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
14 type stacked image sensor with a square pixel array of size 4208 x 3120. It
16 CSI-2.
22 assigned-clocks: true
23 assigned-clock-parents: true
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | mt9p031.txt | 1 * Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
3 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with
5 two-wire serial interface.
8 - compatible: value should be either one among the following
12 - input-clock-frequency: Input clock frequency.
14 - pixel-clock-frequency: Pixel clock frequency.
17 - reset-gpios: Chip reset GPIO
20 Documentation/devicetree/bindings/media/video-interfaces.txt.
30 reset-gpios = <&gpio3 30 0>;
34 input-clock-frequency = <6000000>;
[all …]
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| D | ov7251.txt | 1 * Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor
3 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
8 - compatible: Value should be "ovti,ov7251".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
14 - vdddo-supply: Chip digital IO regulator.
15 - vdda-supply: Chip analog regulator.
16 - vddd-supply: Chip digital core regulator.
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/media/ |
| D | camera-sensor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2 and parallel (BT.601 and BT.656) busses
7 ---------------------------------------------
9 Please see :ref:`transmitter-receiver`.
12 ---------------
14 Camera sensors have an internal clock tree including a PLL and a number of
15 divisors. The clock tree is generally configured by the driver based on a few
16 input parameters that are specific to the hardware:: the external clock frequency
17 and the link frequency. The two parameters generally are obtained from system
20 The reason why the clock frequencies are so important is that the clock signals
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
15 which generate and offers pixel clocks to Display.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
15 which generate and offers pixel clocks to Display.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/ |
| D | cirrus,clps711x-fb.txt | 4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
13 AC bias frequency for a given manufacturer's LCD plate.
14 - cmap-invert : Invert the color levels (Optional).
17 - lcd-supply: Regulator for LCD supply voltage.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | cirrus,clps711x-fb.txt | 4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
13 AC bias frequency for a given manufacturer's LCD plate.
14 - cmap-invert : Invert the color levels (Optional).
17 - lcd-supply: Regulator for LCD supply voltage.
[all …]
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| D | ssd1307fb.txt | 4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/media/ |
| D | camera-sensor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2
7 -----
12 ---------------
14 Camera sensors have an internal clock tree including a PLL and a number of
15 divisors. The clock tree is generally configured by the driver based on a few
16 input parameters that are specific to the hardware:: the external clock frequency
17 and the link frequency. The two parameters generally are obtained from system
20 The reason why the clock frequencies are so important is that the clock signals
21 come out of the SoC, and in many cases a specific frequency is designed to be
[all …]
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| D | csi2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 MIPI CSI-2
8 CSI-2 is a data bus intended for transferring images from cameras to
14 -----------------
16 See :ref:`v4l2-mbus-pixelcode` for details on which media bus formats should
17 be used for CSI-2 interfaces.
20 -------------------
22 CSI-2 transmitter, such as a sensor or a TV tuner, drivers need to
23 provide the CSI-2 receiver with information on the CSI-2 bus
26 (:c:type:`v4l2_subdev_video_ops`->s_stream() callback). These
[all …]
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| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-image-process.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _image-process-controls:
9 The Image Process control class is intended for low-level control of
15 .. _image-process-control-id:
24 Data bus frequency. Together with the media bus pixel code, bus type
25 (clock cycles per sample), the data bus frequency defines the pixel
26 rate (``V4L2_CID_PIXEL_RATE``) in the pixel array (or possibly
28 be calculated from the pixel clock, image width and height and
29 horizontal and vertical blanking. While the pixel rate control may
30 be defined elsewhere than in the subdev containing the pixel array,
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | logicpd-torpedo-37xx-devkit.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 /dts-v1/;
6 #include "logicpd-torpedo-som.dtsi"
7 #include "omap-gpmc-smsc9221.dtsi"
8 #include "logicpd-torpedo-baseboard.dtsi"
12 compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
15 compatible = "regulator-fixed";
16 regulator-name = "vwl1271";
17 regulator-min-microvolt = <1800000>;
18 regulator-max-microvolt = <1800000>;
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| D | clock_source.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
52 * Pixel Clock Parameters structure
54 * when calculating Pixel Clock Dividers for requested Pixel Clock
65 * Display Port HW De spread of Reference Clock related Parameters structure
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
72 /* Average DP Reference clock (in KHz)*/
74 /* DP Reference clock SS percentage
77 /* DP Reference clock SS percentage divider */
82 /*> Requested Pixel Clock
85 /*> Requested Sym Clock (relevant only for display port)*/
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/ |
| D | clock_source.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
52 * Pixel Clock Parameters structure
54 * when calculating Pixel Clock Dividers for requested Pixel Clock
65 * Display Port HW De spread of Reference Clock related Parameters structure
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
72 /* Average DP Reference clock (in KHz)*/
74 /* DP Reference clock SS percentage
77 /* DP Reference clock SS percentage divider */
82 /*> Requested Pixel Clock
85 /*> Requested Sym Clock (relevant only for display port)*/
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | logicpd-torpedo-37xx-devkit.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 /dts-v1/;
6 #include "logicpd-torpedo-som.dtsi"
7 #include "omap-gpmc-smsc9221.dtsi"
8 #include "logicpd-torpedo-baseboard.dtsi"
12 compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
15 compatible = "regulator-fixed";
16 regulator-name = "vwl1271";
17 regulator-min-microvolt = <1800000>;
18 regulator-max-microvolt = <1800000>;
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/85xx/ |
| D | t1042rdb_diu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /*DIU Pixel ClockCR offset in scfg*/
20 /* DIU Pixel Clock bits of the PIXCLKCR */
73 * t1042rdb_set_pixel_clock: program the DIU's clock
74 * @pixclock: pixel clock in ps (pico seconds)
84 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); in t1042rdb_set_pixel_clock()
99 /* Convert pixclock into frequency */ in t1042rdb_set_pixel_clock()
105 * 'pxclk' is the ratio of the platform clock to the pixel clock. in t1042rdb_set_pixel_clock()
107 * range of values is 2-255. in t1042rdb_set_pixel_clock()
112 /* Disable the pixel clock, and set it to non-inverted and no delay */ in t1042rdb_set_pixel_clock()
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/platforms/85xx/ |
| D | t1042rdb_diu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /*DIU Pixel ClockCR offset in scfg*/
20 /* DIU Pixel Clock bits of the PIXCLKCR */
73 * t1042rdb_set_pixel_clock: program the DIU's clock
74 * @pixclock: pixel clock in ps (pico seconds)
84 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); in t1042rdb_set_pixel_clock()
99 /* Convert pixclock into frequency */ in t1042rdb_set_pixel_clock()
105 * 'pxclk' is the ratio of the platform clock to the pixel clock. in t1042rdb_set_pixel_clock()
107 * range of values is 2-255. in t1042rdb_set_pixel_clock()
112 /* Disable the pixel clock, and set it to non-inverted and no delay */ in t1042rdb_set_pixel_clock()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "aptina-pll.h"
27 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
28 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
30 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
31 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
32 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
33 return -EINVAL; in aptina_pll_calculate()
36 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
37 dev_err(dev, "pll: invalid pixel clock frequency.\n"); in aptina_pll_calculate()
[all …]
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| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | video-pxafb.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Author: Jean-Frederic Clere
11 #include <mach/regs-lcd.h>
16 * bits 0 - 3: for LCD panel type:
18 * STN - for passive matrix
19 * DSTN - for dual scan passive matrix
20 * TFT - for active matrix
22 * bits 4 - 9 : for bus width
23 * bits 10-17 : for AC Bias Pin Frequency
25 * bit 19 : for pixel clock edge
[all …]
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| /kernel/linux/linux-5.10/include/media/i2c/ |
| D | mt9p031.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * struct mt9p031_platform_data - MT9P031 platform data
9 * @ext_freq: Input clock frequency
10 * @target_freq: Pixel clock frequency
|