| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy.c | 1 // SPDX-License-Identifier: MIT
25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
28 #define INTEL_CX0_LANE0 BIT(0)
44 return 0; in lane_mask_to_lane()
55 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
66 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
75 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
86 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
99 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
117 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
22 # define PLL_LOCK_COUNT_MASK 0x3f
24 # define PLL_BIAS_COUNT_MASK 0x3f
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
[all …]
|
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
20 #define PLL_OUTCTRL BIT(0)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
37 return 0; in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
24 #define PLL_BASE_DIVM_SHIFT 0
26 #define PLLU_POST_DIVP_MASK 0x1
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
50 #define PLLE_BASE_DIVCML_MASK 0xf
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
24 #define PLL_BASE_DIVM_SHIFT 0
26 #define PLLU_POST_DIVP_MASK 0x1
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
50 #define PLLE_BASE_DIVCML_MASK 0xf
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
20 #define REG_CON0 0
23 #define CON0_BASE_EN BIT(0)
24 #define CON0_PWR_ON BIT(0)
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
43 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
16 # define PLL_OUTCTRL BIT(0)
21 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_MASK 0x3f
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
[all …]
|
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
20 #define PLL_OUTCTRL BIT(0)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
37 return 0; in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "clk-mtk.h"
16 #define REG_CON0 0
19 #define CON0_BASE_EN BIT(0)
20 #define CON0_PWR_ON BIT(0)
26 #define POSTDIV_MASK 0x7
33 * a divider in the PLL feedback loop which consists of 7 bits for the integer
35 * have a 3 bit power-of-two post divider.
57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/meson/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
20 #define PLL_MODE_MASK 0x3
21 #define PLL_MODE_SLOW 0x0
22 #define PLL_MODE_NORM 0x1
23 #define PLL_MODE_DEEP 0x2
24 #define PLL_RK3328_MODE_MASK 0x1
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
32 KP_BAND_MID = 0,
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
42 KP_BAND_MID = 0,
85 struct iproc_pll *pll; member
100 return -EINVAL; in pll_calc_param()
102 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
112 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-pllv3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
16 #define PLL_NUM_OFFSET 0x10
17 #define PLL_DENOM_OFFSET 0x20
18 #define PLL_IMX7_NUM_OFFSET 0x20
19 #define PLL_IMX7_DENOM_OFFSET 0x30
21 #define PLL_VF610_NUM_OFFSET 0x20
22 #define PLL_VF610_DENOM_OFFSET 0x30
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_LOCK (0x1 << 31)
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-pllv3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
17 #define PLL_NUM_OFFSET 0x10
18 #define PLL_DENOM_OFFSET 0x20
19 #define PLL_IMX7_NUM_OFFSET 0x20
20 #define PLL_IMX7_DENOM_OFFSET 0x30
22 #define PLL_VF610_NUM_OFFSET 0x20
23 #define PLL_VF610_DENOM_OFFSET 0x30
25 #define BM_PLL_POWER (0x1 << 12)
26 #define BM_PLL_LOCK (0x1 << 31)
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
[all …]
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
53 * CLK = ----------------------
70 * XCLK The clock rate of the on-chip memory
77 * SCLK Multi-purpose clock
79 * - MCLK and XCLK use the same FB_DIV
80 * - VCLK0 .. VCLK3 use the same FB_DIV
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
8 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
10 int i, ret = 0; in dsi_pll_enable()
16 if (unlikely(pll->pll_on)) in dsi_pll_enable()
17 return 0; in dsi_pll_enable()
20 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
21 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
22 DBG("DSI PLL %s after sequence #%d", in dsi_pll_enable()
29 DRM_ERROR("DSI PLL failed to lock\n"); in dsi_pll_enable()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
20 #define PLL_MODE_MASK 0x3
21 #define PLL_MODE_SLOW 0x0
22 #define PLL_MODE_NORM 0x1
23 #define PLL_MODE_DEEP 0x2
24 #define PLL_RK3328_MODE_MASK 0x1
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/visconti/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti PLL driver
12 #include <linux/clk-provider.h>
17 #include "pll.h"
29 #define PLL_CONF_REG 0x0000
30 #define PLL_CTRL_REG 0x0004
31 #define PLL_FRACMODE_REG 0x0010
32 #define PLL_INTIN_REG 0x0014
33 #define PLL_FRACIN_REG 0x0018
34 #define PLL_REFDIV_REG 0x001c
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
13 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
24 /* PLL enable control bit offset in @con_reg register */
26 /* PLL lock status bit offset in @con_reg register */
36 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
38 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
41 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
52 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
[all …]
|