| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,mu-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 for one processor (A side) to signal the other processor (B side) using
20 different clocks (from each side of the different peripheral buses).
21 Therefore, the MU must synchronize the accesses from one side to the
23 registers (Processor A-side, Processor B-side).
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | fsl,mu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 for one processor to signal the other processor using interrupts.
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | fsl,mu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 for one processor to signal the other processor using interrupts.
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | other.json | 45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
200 "BriefDescription": "Read-write data cache collisions"
255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | other.json | 45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
200 "BriefDescription": "Read-write data cache collisions"
255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | head-nommu.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
25 * ---------------------------
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | head-nommu.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
26 * ---------------------------
29 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
32 * See linux/arch/arm/tools/mach-types for the complete list of machine
47 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
[all …]
|
| /kernel/linux/linux-5.10/tools/testing/selftests/kvm/x86_64/ |
| D | tsc_msrs_test.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "processor.h"
17 #define ROUND(x) ((x + UNITY / 2) & -UNITY)
21 #define GUEST_ASSERT_EQ(a, b) do { \ argument
23 __typeof(b) _b = (b); \
27 #a " == " #b, __LINE__, _a, _b); \
57 * host-side offset and affect both MSRs. in guest_code()
66 * Guest: writes to MSR_IA32_TSC affect both MSRs, so the host-side in guest_code()
73 GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val - HOST_ADJUST); in guest_code()
100 exit_reason_str(vcpu_state(vm, vcpuid)->exit_reason)); in run_vcpu()
[all …]
|
| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-imx-mu-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Based on drivers/mailbox/imx-mailbox.c
50 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
51 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
73 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
78 return ioread32(msi_data->regs + offs); in imx_mu_read()
86 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
87 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
90 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
91 raw_spin_unlock_irqrestore(&msi_data->lock, flags); in imx_mu_xcr_rmw()
[all …]
|
| /kernel/linux/linux-6.6/drivers/eisa/ |
| D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
|
| /kernel/linux/linux-5.10/drivers/eisa/ |
| D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
|
| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | speedstep-lib.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
20 #include "speedstep-lib.h"
22 #define PFX "speedstep-lib: "
31 * GET PROCESSOR CORE SPEED IN KHZ *
34 static unsigned int pentium3_get_frequency(enum speedstep_processor processor) in pentium3_get_frequency() argument
59 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ in pentium3_get_frequency()
61 unsigned int value; /* Front Side Bus speed in MHz */ in pentium3_get_frequency()
74 /* read MSR 0x2a - we only need the low 32 bits */ in pentium3_get_frequency()
76 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); in pentium3_get_frequency()
[all …]
|
| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | speedstep-lib.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
20 #include "speedstep-lib.h"
22 #define PFX "speedstep-lib: "
31 * GET PROCESSOR CORE SPEED IN KHZ *
34 static unsigned int pentium3_get_frequency(enum speedstep_processor processor) in pentium3_get_frequency() argument
59 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ in pentium3_get_frequency()
61 unsigned int value; /* Front Side Bus speed in MHz */ in pentium3_get_frequency()
74 /* read MSR 0x2a - we only need the low 32 bits */ in pentium3_get_frequency()
76 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); in pentium3_get_frequency()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | st,stm32-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 remote processor controller
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
24 processor.
31 reset-names:
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/gadget/udc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
5 # (b) the gadget driver using it.
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
[all …]
|
| /kernel/linux/linux-6.6/Documentation/input/devices/ |
| D | walkera0701.rst | 2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
20 pulses from processor to HF part can be found at pin 2 of this connector,
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
29 __ __ S-video: canon25
34 | [___] | |/| B |\
[all …]
|
| /kernel/linux/linux-5.10/Documentation/input/devices/ |
| D | walkera0701.rst | 2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
20 pulses from processor to HF part can be found at pin 2 of this connector,
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
29 __ __ S-video: canon25
34 | [___] | |/| B |\
[all …]
|
| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
[all …]
|
| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-at91/ |
| D | pm_suspend.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
32 * Side effects: overwrites r7, r8
39 b 2f
45 bne 2b
51 * Side effects: overwrites r7
56 beq 1b
62 * Side effects: overwrites r7
[all …]
|
| /kernel/linux/linux-6.6/Documentation/core-api/ |
| D | cachetlb.rst | 9 describes its intended purpose, and what side effect is expected
12 The side effects described below are stated for a uniprocessor
13 implementation, and what is to happen on that single processor. The
15 definition such that the side effect for a particular interface occurs
25 virtual-->physical address translations obtained from the software
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | rcupdate.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion
15 * For detailed explanation of Read-Copy Update mechanism see -
31 #include <asm/processor.h>
35 #define ULONG_CMP_GE(a, b) (ULONG_MAX / 2 >= (a) - (b)) argument
36 #define ULONG_CMP_LT(a, b) (ULONG_MAX / 2 < (a) - (b)) argument
38 #define USHORT_CMP_GE(a, b) (USHRT_MAX / 2 >= (unsigned short)((a) - (b))) argument
39 #define USHORT_CMP_LT(a, b) (USHRT_MAX / 2 < (unsigned short)((a) - (b))) argument
52 // not-yet-completed RCU grace periods.
56 * same_state_synchronize_rcu - Are two old-state values identical?
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | rcupdate.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion
15 * For detailed explanation of Read-Copy Update mechanism see -
30 #include <asm/processor.h>
33 #define ULONG_CMP_GE(a, b) (ULONG_MAX / 2 >= (a) - (b)) argument
34 #define ULONG_CMP_LT(a, b) (ULONG_MAX / 2 < (a) - (b)) argument
36 #define USHORT_CMP_GE(a, b) (USHRT_MAX / 2 >= (unsigned short)((a) - (b))) argument
37 #define USHORT_CMP_LT(a, b) (USHRT_MAX / 2 < (unsigned short)((a) - (b))) argument
53 * nesting depth, but makes sense only if CONFIG_PREEMPT_RCU -- in other
56 #define rcu_preempt_depth() (current->rcu_read_lock_nesting)
[all …]
|