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/kernel/linux/linux-6.6/drivers/i2c/muxes/
Di2c-mux-reg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/i2c-mux.h>
15 #include <linux/platform_data/i2c-mux-reg.h>
23 static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id) in i2c_mux_reg_set() argument
25 if (!mux->data.reg) in i2c_mux_reg_set()
26 return -EINVAL; in i2c_mux_reg_set()
34 switch (mux->data.reg_size) { in i2c_mux_reg_set()
36 if (mux->data.little_endian) in i2c_mux_reg_set()
37 iowrite32(chan_id, mux->data.reg); in i2c_mux_reg_set()
39 iowrite32be(chan_id, mux->data.reg); in i2c_mux_reg_set()
[all …]
/kernel/linux/linux-5.10/drivers/i2c/muxes/
Di2c-mux-reg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/i2c-mux.h>
15 #include <linux/platform_data/i2c-mux-reg.h>
23 static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id) in i2c_mux_reg_set() argument
25 if (!mux->data.reg) in i2c_mux_reg_set()
26 return -EINVAL; in i2c_mux_reg_set()
34 switch (mux->data.reg_size) { in i2c_mux_reg_set()
36 if (mux->data.little_endian) in i2c_mux_reg_set()
37 iowrite32(chan_id, mux->data.reg); in i2c_mux_reg_set()
39 iowrite32be(chan_id, mux->data.reg); in i2c_mux_reg_set()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mux/
Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
22 reg: true
24 '#mux-control-cells':
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mux/
Dreg-mux.txt1 Generic register bitfield-based multiplexer controller bindings
7 - compatible : should be one of
8 "reg-mux" : if parent device of mux controller is not syscon device
9 "mmio-mux" : if parent device of mux controller is syscon device
10 - #mux-control-cells : <1>
11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
12 pairs, each describing a single mux control.
13 * Standard mux-controller bindings as decribed in mux-controller.txt
16 - idle-states : if present, the state the muxes will have when idle. The
21 pair in the mux-reg-masks array.
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nuvoton/
Dnuvoton-wpcm450.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "arm,arm926ej-s";
29 reg = <0>;
33 clk24m: clock-24mhz {
35 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/drivers/clk/ti/
Dmux.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
23 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_get_parent() local
28 * FIXME need a mux-specific flag to determine if val is bitwise or in ti_clk_mux_get_parent()
34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
35 val &= mux->mask; in ti_clk_mux_get_parent()
37 if (mux->table) { in ti_clk_mux_get_parent()
41 if (mux->table[i] == val) in ti_clk_mux_get_parent()
43 return -EINVAL; in ti_clk_mux_get_parent()
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-mux.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
20 * prepare - clk_prepare only ensures that parents are prepared
21 * enable - clk_enable only ensures that parents are enabled
22 * rate - rate is only affected by parent switching. No clk_set_rate support
23 * parent - parent is adjustable through clk_set_parent
26 static inline u32 clk_mux_readl(struct clk_mux *mux) in clk_mux_readl() argument
28 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
29 return ioread32be(mux->reg); in clk_mux_readl()
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-mux.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
21 * prepare - clk_prepare only ensures that parents are prepared
22 * enable - clk_enable only ensures that parents are enabled
23 * rate - rate is only affected by parent switching. No clk_set_rate support
24 * parent - parent is adjustable through clk_set_parent
27 static inline u32 clk_mux_readl(struct clk_mux *mux) in clk_mux_readl() argument
29 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
30 return ioread32be(mux->reg); in clk_mux_readl()
[all …]
/kernel/linux/linux-5.10/drivers/clk/ti/
Dmux.c6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
31 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_get_parent() local
36 * FIXME need a mux-specific flag to determine if val is bitwise or in ti_clk_mux_get_parent()
42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
43 val &= mux->mask; in ti_clk_mux_get_parent()
45 if (mux->table) { in ti_clk_mux_get_parent()
49 if (mux->table[i] == val) in ti_clk_mux_get_parent()
51 return -EINVAL; in ti_clk_mux_get_parent()
54 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) in ti_clk_mux_get_parent()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmdio-mux-multiplexer.txt3 This is a special case of MDIO mux when MDIO mux is defined as a consumer
4 of a mux producer device. The mux producer can be of any type like mmio mux
5 producer, gpio mux producer or generic register based mux producer.
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
21 In below example the Mux producer and consumer are separate nodes.
25 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-composite-93.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
33 static int imx93_clk_composite_wait_ready(struct clk_hw *hw, void __iomem *reg) in imx93_clk_composite_wait_ready() argument
38 ret = readl_poll_timeout_atomic(reg + STAT_OFFSET, val, !(val & BIT(CCM_BUSY_SHIFT)), in imx93_clk_composite_wait_ready()
50 u32 reg; in imx93_clk_composite_gate_endisable() local
52 if (gate->lock) in imx93_clk_composite_gate_endisable()
53 spin_lock_irqsave(gate->lock, flags); in imx93_clk_composite_gate_endisable()
55 reg = readl(gate->reg); in imx93_clk_composite_gate_endisable()
58 reg &= ~BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
60 reg |= BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
[all …]
Dclk-composite-8m.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
56 int ret = -EINVAL; in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-axg.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
[all …]
Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amlogic/
Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
13 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
Dmeson-axg.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
[all …]
/kernel/linux/linux-5.10/drivers/clk/sprd/
Dmux.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "mux.h"
15 const struct sprd_mux_ssel *mux) in sprd_mux_helper_get_parent() argument
17 unsigned int reg; in sprd_mux_helper_get_parent() local
22 regmap_read(common->regmap, common->reg, &reg); in sprd_mux_helper_get_parent()
23 parent = reg >> mux->shift; in sprd_mux_helper_get_parent()
24 parent &= (1 << mux->width) - 1; in sprd_mux_helper_get_parent()
26 if (!mux->table) in sprd_mux_helper_get_parent()
29 num_parents = clk_hw_get_num_parents(&common->hw); in sprd_mux_helper_get_parent()
[all …]
/kernel/linux/linux-6.6/drivers/clk/sprd/
Dmux.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "mux.h"
15 const struct sprd_mux_ssel *mux) in sprd_mux_helper_get_parent() argument
17 unsigned int reg; in sprd_mux_helper_get_parent() local
22 regmap_read(common->regmap, common->reg, &reg); in sprd_mux_helper_get_parent()
23 parent = reg >> mux->shift; in sprd_mux_helper_get_parent()
24 parent &= (1 << mux->width) - 1; in sprd_mux_helper_get_parent()
26 if (!mux->table) in sprd_mux_helper_get_parent()
29 num_parents = clk_hw_get_num_parents(&common->hw); in sprd_mux_helper_get_parent()
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-composite-8m.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
56 int ret = -EINVAL; in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/aspeed/
Daspeed-bmc-ampere-mtjade.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
12 * i2c bus 50-57 assigned to NVMe slot 0-7
24 * i2c bus 60-67 assigned to NVMe slot 8-15
36 * i2c bus 70-77 assigned to NVMe slot 16-23
48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1
55 stdout-path = &uart5;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
[all …]

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