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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek STAR Ethernet MAC Controller
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
[all …]
Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
[all …]
Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
24 possible values from "txclk", "clk_125" or "clkgen".
26 - sti-ethclk: this is the phy clock.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.txt9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
14 Should be "macirq" for the main MAC IRQ
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
[all …]
Dimx-dwmac.txt1 IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
9 - compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
10 and "snps,dwmac-5.10a" to select IP version.
11 - clocks: Must contain a phandle for each entry in clock-names.
12 - clock-names: Should be "stmmaceth" for the host clock.
13 Should be "pclk" for the MAC apb clock.
14 Should be "ptp_ref" for the MAC timer clock.
15 Should be "tx" for the MAC RGMII TX clock:
17 - "mem" clock is required for imx8dxl platform.
18 - "mem" clock is not required for imx8mp platform.
[all …]
Dsti-dwmac.txt10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 MAC can generate it.
23 - st,tx-retime-src: This specifies which clk is wired up to the mac for
25 posssible values from "txclk", "clk_125" or "clkgen".
[all …]
Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek STAR Ethernet MAC Controller
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: "ethernet-controller.yaml#"
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
103 /* list of clocks required for mac */
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
[all …]
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
46 * RMII | 1 | 0 | 0 | n/a |
47 *------------------------------------------
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Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
18 #include <linux/clk.h>
43 * ------------------------------------------------
46 * ------------------------------------------------
48 *| | clk-125/txclk | txclk |
49 * ------------------------------------------------
51 *| | clk-125/txclk | clkgen |
53 * ------------------------------------------------
[all …]
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
50 /* Bypass (= 0, the signal from the GPIO input directly connects to the
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
94 struct clk *rgmii_tx_clk;
97 struct clk *timing_adj_clk;
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
119 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk()
[all …]
Ddwmac-rk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
12 #include <linux/clk.h>
74 struct clk *clk_mac;
75 struct clk *clk_phy;
106 struct device *dev = &bsp_priv->pdev->dev; in px30_set_to_rmii()
108 if (IS_ERR(bsp_priv->grf)) { in px30_set_to_rmii()
113 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
76 /* list of clocks required for mac */
83 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
84 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
88 * only in RMII(when MAC provides the reference clock), and useless for in mt2712_set_interface()
89 * RGMII/MII/RMII(when PHY provides the reference clock). in mt2712_set_interface()
91 * configured, equals to (plat->variant->num_clks - 1) in default for all the case, in mt2712_set_interface()
94 plat->num_clks_to_config = plat->variant->num_clks - 1; in mt2712_set_interface()
97 switch (plat->phy_mode) { in mt2712_set_interface()
102 if (plat->rmii_clk_from_mac) in mt2712_set_interface()
[all …]
Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
18 #include <linux/clk.h>
44 * ------------------------------------------------
47 * ------------------------------------------------
49 *| | clk-125/txclk | txclk |
50 * ------------------------------------------------
52 *| | clk-125/txclk | clkgen |
54 * ------------------------------------------------
[all …]
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
38 *------------------------------------------
40 *------------------------------------------
42 *------------------------------------------
44 *------------------------------------------
46 *------------------------------------------
47 * RMII | 1 | 0 | 0 | n/a |
48 *------------------------------------------
[all …]
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
50 /* Bypass (= 0, the signal from the GPIO input directly connects to the
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
83 struct clk *rgmii_tx_clk;
86 struct clk *timing_adj_clk;
101 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
105 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
108 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk()
[all …]
Ddwmac-rk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
12 #include <linux/clk.h>
49 struct clk *clk_mac;
50 struct clk *gmac_clkin;
51 struct clk *mac_clk_rx;
52 struct clk *mac_clk_tx;
53 struct clk *clk_mac_ref;
[all …]
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
26 /* General notes on dwmac-sun8i:
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
37 * @soc_has_internal_phy: Does the MAC embed an internal PHY
38 * @support_mii: Does the MAC handle MII
39 * @support_rmii: Does the MAC handle RMII
40 * @support_rgmii: Does the MAC handle RGMII
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Ddp83td510.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Bit 7 - mii_interrupt, active high. Clears on read.
17 * This differs from the DP83TD510E datasheet (2020) which states this bit
40 * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
41 * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
42 * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
43 * features for 100BASE-T1 automotive Ethernet PHYs"
60 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83td510_config_intr()
112 phydev->speed = SPEED_UNKNOWN; in dp83td510_read_status()
113 phydev->duplex = DUPLEX_UNKNOWN; in dp83td510_read_status()
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/socionext/
Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
38 /* MAC Register Group */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
84 /* RMII Bridge Register Group */
93 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
98 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/socionext/
Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
37 /* MAC Register Group */
40 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
41 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
83 /* RMII Bridge Register Group */
92 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
97 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/actions/
Dowl-emac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semi Owl SoCs Ethernet MAC driver
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
19 #include "owl-emac.h"
27 return readl(priv->base + reg); in owl_emac_reg_read()
32 writel(data, priv->base + reg); in owl_emac_reg_write()
63 return priv->netdev->dev.parent; in owl_emac_get_dev()
84 * unexpected side effect (MAC hardware bug?!) where some bits in the in owl_emac_irq_disable()
129 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in owl_emac_dma_map_tx()
[all …]

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