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/kernel/linux/linux-6.6/include/drm/display/
Ddrm_dsc.h1 /* SPDX-License-Identifier: MIT
48 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
70 * struct drm_dsc_config - Parameters required to configure DSC
78 * Bits per component for previous reconstructed line buffer
82 * @bits_per_component: Bits per component to code (8/10/12)
87 * Flag to indicate if RGB - YCoCg conversion is needed
92 * @slice_count: Number fo slices per line used by the DSC encoder
96 * @slice_width: Width of each slice in pixels
100 * @slice_height: Slice height in pixels
127 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
[all …]
/kernel/linux/linux-5.10/include/drm/
Ddrm_dsc.h1 /* SPDX-License-Identifier: MIT
48 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
70 * struct drm_dsc_config - Parameters required to configure DSC
78 * Bits per component for previous reconstructed line buffer
82 * @bits_per_component: Bits per component to code (8/10/12)
87 * Flag to indicate if RGB - YCoCg conversion is needed
92 * @slice_count: Number fo slices per line used by the DSC encoder
96 * @slice_width: Width of each slice in pixels
100 * @slice_height: Slice height in pixels
127 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
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/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power9/
Dother.json25 "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice"
60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to …
125 "BriefDescription": "TEND latency per thread"
175 "BriefDescription": "Ic line invalidated"
190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie…
200 "BriefDescription": "Read-write data cache collisions"
235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/
Dother.json25 "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice"
60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to …
125 "BriefDescription": "TEND latency per thread"
175 "BriefDescription": "Ic line invalidated"
190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie…
200 "BriefDescription": "Read-write data cache collisions"
235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
[all …]
/kernel/linux/linux-6.6/Documentation/scheduler/
Dsched-bwc.rst7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
23 within each of these updates is tunable and described as the "slice".
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
46 the cost of missing deadlines when all the odds line up. However, it
66 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
69 ----------
75 :ref:`Documentation/admin-guide/cgroup-v2.rst <cgroup-v2-cpu>`.
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/kernel/linux/linux-5.10/drivers/gpu/drm/
Ddrm_dsc.c1 // SPDX-License-Identifier: MIT
33 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
34 * for DisplayPort as per the DP 1.4 spec.
47 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
48 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
53 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
81 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
82 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
83 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
88 pps_payload->pps_3 = in drm_dsc_pps_payload_pack()
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/kernel/linux/linux-6.6/drivers/misc/cxl/
Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <misc/cxl-base.h>
45 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n"); in cxl_afu_slbia()
46 return -EBUSY; in cxl_afu_slbia()
51 if (!cxl_ops->link_ok(afu->adapter, afu)) in cxl_afu_slbia()
52 return -EIO; in cxl_afu_slbia()
62 if (ctx->mm != mm) in _cxl_slbia()
65 pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__, in _cxl_slbia()
66 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe); in _cxl_slbia()
68 spin_lock_irqsave(&ctx->sste_lock, flags); in _cxl_slbia()
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/kernel/linux/linux-5.10/drivers/misc/cxl/
Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <misc/cxl-base.h>
44 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n"); in cxl_afu_slbia()
45 return -EBUSY; in cxl_afu_slbia()
50 if (!cxl_ops->link_ok(afu->adapter, afu)) in cxl_afu_slbia()
51 return -EIO; in cxl_afu_slbia()
61 if (ctx->mm != mm) in _cxl_slbia()
64 pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__, in _cxl_slbia()
65 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe); in _cxl_slbia()
67 spin_lock_irqsave(&ctx->sste_lock, flags); in _cxl_slbia()
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/kernel/linux/linux-6.6/drivers/media/platform/samsung/s5p-mfc/
Dregs-mfc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
16 #define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
74 /* overlap transform line */
84 /* VC-1 decoding */
189 #define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
191 #define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
193 #define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
195 #define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
265 #define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
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/kernel/linux/linux-5.10/drivers/media/platform/s5p-mfc/
Dregs-mfc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
16 #define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
74 /* overlap transform line */
84 /* VC-1 decoding */
189 #define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
191 #define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
193 #define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
195 #define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
265 #define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
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/kernel/linux/linux-6.6/block/partitions/
Dmsdos.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 1991-1998 Linus Torvalds
9 * in the early extended-partition checks and added DM partitions
16 * More flexible handling of extended partitions - aeb, 950831
20 * Re-organised Feb 1998 Russell King
43 return (sector_t)get_unaligned_le32(&p->nr_sects); in nr_sects()
48 return (sector_t)get_unaligned_le32(&p->start_sect); in start_sect()
53 return (p->sys_ind == DOS_EXTENDED_PARTITION || in is_extended_partition()
54 p->sys_ind == WIN98_EXTENDED_PARTITION || in is_extended_partition()
55 p->sys_ind == LINUX_EXTENDED_PARTITION); in is_extended_partition()
[all …]
/kernel/linux/linux-5.10/block/partitions/
Dmsdos.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 1991-1998 Linus Torvalds
9 * in the early extended-partition checks and added DM partitions
16 * More flexible handling of extended partitions - aeb, 950831
20 * Re-organised Feb 1998 Russell King
43 return (sector_t)get_unaligned_le32(&p->nr_sects); in nr_sects()
48 return (sector_t)get_unaligned_le32(&p->start_sect); in start_sect()
53 return (p->sys_ind == DOS_EXTENDED_PARTITION || in is_extended_partition()
54 p->sys_ind == WIN98_EXTENDED_PARTITION || in is_extended_partition()
55 p->sys_ind == LINUX_EXTENDED_PARTITION); in is_extended_partition()
[all …]
/kernel/linux/linux-6.6/Documentation/accel/qaic/
Dqaic.rst1 .. SPDX-License-Identifier: GPL-2.0-only
18 non-empty and generate MSIs at a rate equivalent to the speed of the
21 MSIs per second. It has been observed that most systems cannot tolerate this
26 QAIC receives an IRQ, it disables that line. This prevents the interrupt
30 line remains disabled during this time. If no activity is detected, QAIC exits
31 polling mode and reenables the IRQ line.
34 generates 100k IRQs per second (per /proc/interrupts) is reduced to roughly 64
49 QAIC handles and enforces the required little endianness and 64-bit alignment,
91 This IOCTL allows userspace to slice a BO in preparation for sending the BO
98 call is non-blocking. Success only indicates that the BOs have been queued
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,merge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
24 - enum:
25 - mediatek,mt8173-disp-merge
26 - mediatek,mt8195-disp-merge
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/kernel/linux/linux-5.10/drivers/dma/dw/
Didma32.c1 // SPDX-License-Identifier: GPL-2.0
21 cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf); in idma32_initialize_chan()
22 cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf); in idma32_initialize_chan()
24 /* Request line extension (2 bits) */ in idma32_initialize_chan()
25 cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3); in idma32_initialize_chan()
26 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3); in idma32_initialize_chan()
57 if (bytes > dwc->block_size) { in idma32_bytes2block()
58 block = dwc->block_size; in idma32_bytes2block()
59 *len = dwc->block_size; in idma32_bytes2block()
75 struct dma_slave_config *sconfig = &dwc->dma_sconfig; in idma32_prepare_ctllo()
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/kernel/linux/linux-6.6/tools/perf/Documentation/
Dperf-report.txt1 perf-report(1)
5 ----
6 perf-report - Read perf.data (created by perf record) and display the profile
9 --------
11 'perf report' [-i <file> | --input=file]
14 -----------
19 -------
20 -i::
21 --input=::
24 -v::
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/kernel/linux/linux-5.10/tools/perf/Documentation/
Dperf-report.txt1 perf-report(1)
5 ----
6 perf-report - Read perf.data (created by perf record) and display the profile
9 --------
11 'perf report' [-i <file> | --input=file]
14 -----------
19 -------
20 -i::
21 --input=::
24 -v::
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c52 /* Need to account for padding due to pixel-to-symbol packing
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
70 /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit symbol size) in apply_128b_132b_stream_overhead()
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
96 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
97 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
98 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
100 switch (timing->display_color_depth) { in dc_bandwidth_in_kbps_from_timing()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_engine_cs.c47 * on HSW) - so the final size, including the extra state required for the
144 * intel_engine_context_size() - return the size of the context for an engine
159 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
166 switch (INTEL_GEN(gt->i915)) { in intel_engine_context_size()
168 MISSING_CASE(INTEL_GEN(gt->i915)); in intel_engine_context_size()
180 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
203 drm_dbg(&gt->i915->drm, in intel_engine_context_size()
205 INTEL_GEN(gt->i915), cxt_size * 64, in intel_engine_context_size()
206 cxt_size - 1); in intel_engine_context_size()
221 if (INTEL_GEN(gt->i915) < 8) in intel_engine_context_size()
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/kernel/linux/linux-5.10/include/uapi/drm/
Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
126 I915_ENGINE_CLASS_INVALID = -1
139 #define I915_ENGINE_CLASS_INVALID_NONE -1
[all …]
/kernel/linux/linux-5.10/tools/include/uapi/drm/
Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
126 I915_ENGINE_CLASS_INVALID = -1
139 #define I915_ENGINE_CLASS_INVALID_NONE -1
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/kernel/linux/linux-6.6/drivers/dma/dw/
Didma32.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013,2018,2020-2021 Intel Corporation
38 struct device *slave = dwc->chan.slave; in idma32_get_slave_devfn()
43 return to_pci_dev(slave)->devfn; in idma32_get_slave_devfn()
48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar()
58 value |= dwc->chan.chan_id; in idma32_initialize_chan_xbar()
63 value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
69 switch (dwc->direction) { in idma32_initialize_chan_xbar()
80 * Memory-to-Memory and Device-to-Device are ignored for now. in idma32_initialize_chan_xbar()
82 * For Memory-to-Memory transfers we would need to set mode in idma32_initialize_chan_xbar()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_hdmi.c3 * Copyright © 2006-2009 Intel Corporation
64 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); in intel_hdmi_to_i915()
75 drm_WARN(&dev_priv->drm, in assert_hdmi_port_disabled()
76 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
84 drm_WARN(&dev_priv->drm, in assert_hdmi_transcoder_func_disabled()
206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_write_infoframe()
210 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_read_infoframe()
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_infoframes_enabled()
261 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in g4x_infoframes_enabled()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c46 if (timing->flags.DSC) { in dc_dsc_bandwidth_in_kbps_from_timing()
47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); in dc_dsc_bandwidth_in_kbps_from_timing()
52 switch (timing->display_color_depth) { in dc_dsc_bandwidth_in_kbps_from_timing()
77 kbps = timing->pix_clk_100hz / 10; in dc_dsc_bandwidth_in_kbps_from_timing()
80 if (timing->flags.Y_ONLY != 1) { in dc_dsc_bandwidth_in_kbps_from_timing()
83 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in dc_dsc_bandwidth_in_kbps_from_timing()
85 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in dc_dsc_bandwidth_in_kbps_from_timing()
217 dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); in dsc_bpp_increment_div_from_dpcd()
234 if (!dsc->ctx->dc->debug.disable_dsc) in get_dsc_enc_caps()
235 dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); in get_dsc_enc_caps()
[all …]
/kernel/linux/linux-5.10/block/
Dbfq-iosched.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <linux/blk-cgroup.h>
13 #include "blk-cgroup-rwstat.h"
31 * Soft real-time applications are extremely more latency sensitive
32 * than interactive ones. Over-raise the weight of the former to
40 * struct bfq_service_tree - per ioprio_class service tree.
42 * Each service tree represents a B-WF2Q+ scheduler on its own. Each
65 * struct bfq_sched_data - multi-class scheduler.
75 * queue requests are served according to B-WF2Q+.
80 * before the current in-service entity is expired, 2) the in-service
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