Home
last modified time | relevance | path

Searched +full:spi +full:- +full:bcm +full:- +full:qspi (Results 1 – 25 of 59) sorted by relevance

123

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.txt1 Broadcom SPI controller
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
9 io with 3-byte and 4-byte addressing support.
14 use SPI protocol.
18 - #address-cells:
19 Must be <1>, as required by generic SPI binding.
21 - #size-cells:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-brcmstb-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "spi-bcm-qspi.h"
13 { .compatible = "brcm,spi-brcmstb-qspi" },
14 { .compatible = "brcm,spi-brcmstb-mspi" },
42 MODULE_DESCRIPTION("Broadcom SPI driver for settop SoC");
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for kernel SPI drivers.
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
16 # SPI master controller drivers (bus)
[all …]
Dspi-iproc-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "spi-bcm-qspi.h"
33 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_get_l2_int_status()
38 if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4))) in bcm_iproc_qspi_get_l2_int_status()
58 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_int_ack()
64 bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4)); in bcm_iproc_qspi_int_ack()
73 void __iomem *mmio = priv->int_reg; in bcm_iproc_qspi_int_set()
78 spin_lock_irqsave(&priv->soclock, flags); in bcm_iproc_qspi_int_set()
80 val = bcm_qspi_readl(priv->big_endian, mmio); in bcm_iproc_qspi_int_set()
87 bcm_qspi_writel(priv->big_endian, val, mmio); in bcm_iproc_qspi_int_set()
[all …]
Dspi-bcm-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
21 #include <linux/spi/spi.h>
22 #include <linux/mtd/spi-nor.h>
25 #include "spi-bcm-qspi.h"
234 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
236 return qspi->bspi_mode; in has_bspi()
239 /* hardware supports spcr3 and fast baud-rate */
240 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
242 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-brcmstb-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "spi-bcm-qspi.h"
13 { .compatible = "brcm,spi-brcmstb-qspi" },
14 { .compatible = "brcm,spi-brcmstb-mspi" },
42 MODULE_DESCRIPTION("Broadcom SPI driver for settop SoC");
Dspi-iproc-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "spi-bcm-qspi.h"
33 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_get_l2_int_status()
38 if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4))) in bcm_iproc_qspi_get_l2_int_status()
58 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_int_ack()
64 bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4)); in bcm_iproc_qspi_int_ack()
73 void __iomem *mmio = priv->int_reg; in bcm_iproc_qspi_int_set()
78 spin_lock_irqsave(&priv->soclock, flags); in bcm_iproc_qspi_int_set()
80 val = bcm_qspi_readl(priv->big_endian, mmio); in bcm_iproc_qspi_int_set()
87 bcm_qspi_writel(priv->big_endian, val, mmio); in bcm_iproc_qspi_int_set()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for kernel SPI drivers.
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
16 # SPI master controller drivers (bus)
[all …]
Dspi-bcm-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
21 #include <linux/spi/spi.h>
22 #include <linux/mtd/spi-nor.h>
25 #include "spi-bcm-qspi.h"
171 * to TXRAM and RXRAM when used as 32-bit registers respectively
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
260 /* hardware supports spcr3 and fast baud-rate */
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm5301x.dtsi9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
30 compatible = "arm,cortex-a9-pmu";
37 #address-cells = <1>;
38 #size-cells = <1>;
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
[all …]
Dbcm53340-ubnt-unifi-switch8.dts9 /dts-v1/;
11 #include "bcm-hr2.dtsi"
14 compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2";
33 &qspi {
35 bspi-sel = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 spi-max-frequency = <12500000>;
43 spi-cpol;
44 spi-cpha;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/brcm/
Dbcm7125.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <202500000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7420.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
Dbcm7360.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
Dbcm7362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/brcm/
Dbcm7125.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <202500000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7420.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
Dbcm7360.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
Dbcm7362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm53340-ubnt-unifi-switch8.dts9 /dts-v1/;
11 #include "bcm-hr2.dtsi"
14 compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2";
33 &qspi {
35 bspi-sel = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 spi-max-frequency = <12500000>;
43 spi-cpol;
44 spi-cpha;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]

123