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Searched +full:spi +full:- +full:nsp +full:- +full:qspi (Results 1 – 25 of 33) sorted by relevance

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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.txt1 Broadcom SPI controller
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
9 io with 3-byte and 4-byte addressing support.
14 use SPI protocol.
18 - #address-cells:
19 Must be <1>, as required by generic SPI binding.
21 - #size-cells:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm5301x.dtsi9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
30 compatible = "arm,cortex-a9-pmu";
37 #address-cells = <1>;
38 #size-cells = <1>;
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
[all …]
Dbcm958522er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
[all …]
Dbcm958525er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
Dbcm958622hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
Dbcm958525xmc.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
76 temperature-sensor@4c {
97 nand-on-flash-bbt;
[all …]
Dbcm958625hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
60 i2c-bus = <&i2c0>;
61 mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
[all …]
Dbcm958623hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
Dbcm988312hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
Dbcm958625k.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
39 compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";
42 stdout-path = "serial0:115200n8";
75 nand-on-flash-bbt;
77 #address-cells = <1>;
78 #size-cells = <1>;
80 nand-ecc-strength = <24>;
81 nand-ecc-step-size = <1024>;
83 brcm,nand-oob-sector-size = <27>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
[all …]
Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
Dbcm958625hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm58625", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
60 i2c-bus = <&i2c0>;
61 mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
[all …]
Dbcm958623hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm58623", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
Dbcm958622hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm58622", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
Dbcm988312hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm88312", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
Dbcm958522er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm58522", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
Dbcm958525er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
Dbcm958625k.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
39 compatible = "brcm,bcm58625", "brcm,nsp";
42 stdout-path = "serial0:115200n8";
75 nand-on-flash-bbt;
77 #address-cells = <1>;
78 #size-cells = <1>;
80 nand-ecc-strength = <24>;
81 nand-ecc-step-size = <1024>;
83 brcm,nand-oob-sector-size = <27>;
[all …]
Dbcm958525xmc.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
76 temperature-sensor@4c {
97 nand-on-flash-bbt;
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-iproc-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "spi-bcm-qspi.h"
33 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_get_l2_int_status()
38 if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4))) in bcm_iproc_qspi_get_l2_int_status()
58 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_int_ack()
64 bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4)); in bcm_iproc_qspi_int_ack()
73 void __iomem *mmio = priv->int_reg; in bcm_iproc_qspi_int_set()
78 spin_lock_irqsave(&priv->soclock, flags); in bcm_iproc_qspi_int_set()
80 val = bcm_qspi_readl(priv->big_endian, mmio); in bcm_iproc_qspi_int_set()
87 bcm_qspi_writel(priv->big_endian, val, mmio); in bcm_iproc_qspi_int_set()
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-iproc-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "spi-bcm-qspi.h"
33 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_get_l2_int_status()
38 if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4))) in bcm_iproc_qspi_get_l2_int_status()
58 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_int_ack()
64 bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4)); in bcm_iproc_qspi_int_ack()
73 void __iomem *mmio = priv->int_reg; in bcm_iproc_qspi_int_set()
78 spin_lock_irqsave(&priv->soclock, flags); in bcm_iproc_qspi_int_set()
80 val = bcm_qspi_readl(priv->big_endian, mmio); in bcm_iproc_qspi_int_set()
87 bcm_qspi_writel(priv->big_endian, val, mmio); in bcm_iproc_qspi_int_set()
[all …]

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