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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dnuvoton,npcm-reset.txt1 Nuvoton NPCM Reset controller
4 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
5 - reg : specifies physical base address and size of the register.
6 - #reset-cells: must be set to 2
9 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
10 NPCM7xx contain four software reset that represent numbers 1 to 4.
12 If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
16 compatible = "nuvoton,npcm750-reset";
18 #reset-cells = <2>;
19 nuvoton,sw-reset-number = <2>;
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Reset controller
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
28 nuvoton,sw-reset-number:
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_ctl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
26 * struct dpu_hw_stage_cfg - blending stage cfg
42 * @stream_sel: Stream selection for multi-stream interfaces
56 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
61 * kickoff hw operation for Sw controlled interfaces
62 * DSI cmd mode and WB interface are SW controlled
75 * kickoff prepare is in progress hw operation for sw
77 * are SW controlled
156 * @dspp_sub_blk : DSPP sub-block index
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/kernel/linux/linux-6.6/drivers/thunderbolt/
Dlc.c1 // SPDX-License-Identifier: GPL-2.0
14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
15 * @sw: Switch whose UUID is read
18 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid) in tb_lc_read_uuid() argument
20 if (!sw->cap_lc) in tb_lc_read_uuid()
21 return -EINVAL; in tb_lc_read_uuid()
22 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 static int read_lc_desc(struct tb_switch *sw, u32 *desc) in read_lc_desc() argument
27 if (!sw->cap_lc) in read_lc_desc()
28 return -EINVAL; in read_lc_desc()
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Dtb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - bus logic (NHI independent)
12 #include <linux/nvmem-provider.h>
30 * struct tb_nvm - Structure holding NVM information
32 * @major: Major version number of the active NVM portion
33 * @minor: Minor version number of the active NVM portion
37 * @non_active: Non-active portion NVMem device
42 * @buf_data_size: Number of bytes actually consumed by the new NVM
78 * enum tb_switch_tmu_mode - TMU mode
80 * @TB_SWITCH_TMU_MODE_LOWRES: Uni-directional, normal mode
[all …]
Ddma_port.c1 // SPDX-License-Identifier: GPL-2.0
48 * struct tb_dma_port - DMA control port
49 * @sw: Switch the DMA port belongs to
50 * @port: Switch port number where DMA capability is found
55 struct tb_switch *sw; member
68 u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63); in dma_port_match()
70 if (pkg->frame.eof == TB_CFG_PKG_ERROR) in dma_port_match()
72 if (pkg->frame.eof != req->response_type) in dma_port_match()
74 if (route != tb_cfg_get_route(req->request)) in dma_port_match()
76 if (pkg->frame.size != req->response_size) in dma_port_match()
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Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
37 static struct nvm_auth_status *__nvm_get_auth_status(const struct tb_switch *sw) in __nvm_get_auth_status() argument
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
49 static void nvm_get_auth_status(const struct tb_switch *sw, u32 *status) in nvm_get_auth_status() argument
54 st = __nvm_get_auth_status(sw); in nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
60 static void nvm_set_auth_status(const struct tb_switch *sw, u32 status) in nvm_set_auth_status() argument
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
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Dicm.c1 // SPDX-License-Identifier: GPL-2.0
4 * the Thunderbolt host controller performing most of the low-level
53 * struct usb4_switch_nvm_auth - Holds USB4 NVM_AUTH status
65 * struct icm - Internal connection manager private data
74 * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported)
81 * @cio_reset: Trigger CIO reset
158 if (!ep->len) in parse_intel_vss()
160 if (ep_name + ep->len > end) in parse_intel_vss()
163 if (ep->type == EP_NAME_INTEL_VSS) in parse_intel_vss()
164 return (const struct intel_vss *)ep->data; in parse_intel_vss()
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/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x540.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
31 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X540()
32 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X540()
35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; in ixgbe_get_invariants_X540()
37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; in ixgbe_get_invariants_X540()
38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; in ixgbe_get_invariants_X540()
39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; in ixgbe_get_invariants_X540()
40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; in ixgbe_get_invariants_X540()
41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; in ixgbe_get_invariants_X540()
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x540.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
31 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X540()
32 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X540()
35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; in ixgbe_get_invariants_X540()
37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; in ixgbe_get_invariants_X540()
38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; in ixgbe_get_invariants_X540()
39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; in ixgbe_get_invariants_X540()
40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; in ixgbe_get_invariants_X540()
41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; in ixgbe_get_invariants_X540()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_ctl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
26 * struct dpu_hw_stage_cfg - blending stage cfg
41 * @stream_sel: Stream selection for multi-stream interfaces
51 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
56 * kickoff hw operation for Sw controlled interfaces
57 * DSI cmd mode and WB interface are SW controlled
63 * kickoff prepare is in progress hw operation for sw
65 * are SW controlled
123 int (*reset)(struct dpu_hw_ctl *c); member
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/kernel/linux/linux-6.6/include/linux/mfd/
Daltera-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
27 * the number of GPIO in each register. We then need to multiply
39 #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
41 #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
45 #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
46 #define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */
55 #define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */
56 #define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */
60 #define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */
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/kernel/linux/linux-5.10/include/linux/mfd/
Daltera-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
27 * the number of GPIO in each register. We then need to multiply
39 #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
41 #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
45 #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
46 #define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */
55 #define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */
56 #define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */
60 #define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */
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/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_timer.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
48 * - MSFTRST register is introduced in Nuclei N Core version 1.3(\ref __NUCLEI_N_REV >= 0x0103)
49 …* - MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(\ref __NUCLEI_N_RE…
50 …* - CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(\ref _…
55 __IOM uint32_t RESERVED0[0x3F8]; /*!< Offset: 0x010 - 0xFEC Reserved */
56 …2_t MSFTRST; /*!< Offset: 0xFF0 (R/W) System Timer Software Core Reset Register */
59 …__IOM uint32_t MSIP; /*!< Offset: 0xFFC (R/W) System Timer SW interrupt Regist…
79 … (0x80000A5FUL) /*!< SysTick Timer Software Reset Request Key */
102 * - Load value is 64bits wide.
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/kernel/linux/linux-6.6/include/linux/soc/ti/
Dk3-ringacc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum k3_ring_mode - &struct k3_ring_cfg mode
20 * @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
24 * controls the entire state of the queue, and SW has no directly control,
26 * This is particularly useful when more than one SW or HW entity can be
41 * enum k3_ring_size - &struct k3_ring_cfg elm_size
60 * enum k3_ring_cfg - RA ring configuration structure
62 * @size: Ring size, number of elements
86 #define K3_RINGACC_RING_ID_ANY (-1)
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/kernel/linux/linux-5.10/include/linux/soc/ti/
Dk3-ringacc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum k3_ring_mode - &struct k3_ring_cfg mode
20 * @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
24 * controls the entire state of the queue, and SW has no directly control,
26 * This is particularly useful when more than one SW or HW entity can be
41 * enum k3_ring_size - &struct k3_ring_cfg elm_size
60 * enum k3_ring_cfg - RA ring configuration structure
62 * @size: Ring size, number of elements
79 #define K3_RINGACC_RING_ID_ANY (-1)
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/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
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/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
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/kernel/linux/linux-5.10/drivers/thunderbolt/
Ddma_port.c1 // SPDX-License-Identifier: GPL-2.0
48 * struct tb_dma_port - DMA control port
49 * @sw: Switch the DMA port belongs to
50 * @port: Switch port number where DMA capability is found
55 struct tb_switch *sw; member
68 u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63); in dma_port_match()
70 if (pkg->frame.eof == TB_CFG_PKG_ERROR) in dma_port_match()
72 if (pkg->frame.eof != req->response_type) in dma_port_match()
74 if (route != tb_cfg_get_route(req->request)) in dma_port_match()
76 if (pkg->frame.size != req->response_size) in dma_port_match()
[all …]
Dicm.c1 // SPDX-License-Identifier: GPL-2.0
4 * the Thunderbolt host controller performing most of the low-level
53 * struct icm - Internal connection manager private data
62 * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported)
67 * @cio_reset: Trigger CIO reset
75 * @xdomain_connected - Handle XDomain connected ICM message
76 * @xdomain_disconnected - Handle XDomain disconnected ICM message
142 if (!ep->len) in parse_intel_vss()
144 if (ep_name + ep->len > end) in parse_intel_vss()
147 if (ep->type == EP_NAME_INTEL_VSS) in parse_intel_vss()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_lib.c1 // SPDX-License-Identifier: GPL-2.0
13 * ice_vsi_type_str - maps VSI type enum to string equivalents
33 * ice_vsi_ctrl_all_rx_rings - Start or stop a VSI's Rx rings
47 for (i = 0; i < vsi->num_rxq; i++) in ice_vsi_ctrl_all_rx_rings()
50 ice_flush(&vsi->back->hw); in ice_vsi_ctrl_all_rx_rings()
52 for (i = 0; i < vsi->num_rxq; i++) { in ice_vsi_ctrl_all_rx_rings()
62 * ice_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the VSI
70 struct ice_pf *pf = vsi->back; in ice_vsi_alloc_arrays()
76 vsi->tx_rings = devm_kcalloc(dev, vsi->alloc_txq, in ice_vsi_alloc_arrays()
77 sizeof(*vsi->tx_rings), GFP_KERNEL); in ice_vsi_alloc_arrays()
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/kernel/linux/linux-5.10/arch/alpha/kernel/
Dsignal.c1 // SPDX-License-Identifier: GPL-2.0
7 * 1997-11-02 Modified for POSIX.1b signals by Richard Henderson
69 __get_user(new_ka.sa.sa_handler, &act->sa_handler) || in SYSCALL_DEFINE3()
70 __get_user(new_ka.sa.sa_flags, &act->sa_flags) || in SYSCALL_DEFINE3()
71 __get_user(mask, &act->sa_mask)) in SYSCALL_DEFINE3()
72 return -EFAULT; in SYSCALL_DEFINE3()
81 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || in SYSCALL_DEFINE3()
82 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || in SYSCALL_DEFINE3()
83 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) in SYSCALL_DEFINE3()
84 return -EFAULT; in SYSCALL_DEFINE3()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/sun/
Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GREG_SWRESET 0x000UL /* Software Reset */
21 /* Global reset register. */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
[all …]

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