Searched +full:tegra114 +full:- +full:i2c (Results 1 – 25 of 35) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 1 NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. 4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or 5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". 6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be 7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is 10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C 11 controller. This only support master mode of I2C communication. Register 12 interface/offset and interrupts handling are different than generic I2C 13 controller. Driver of DVC I2C controller is only compatible with 14 "nvidia,tegra20-i2c-dvc". [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 - Thierry Reding <thierry.reding@gmail.com> 9 - Jon Hunter <jonathanh@nvidia.com> 11 title: NVIDIA Tegra I2C controller driver 16 - description: Tegra20 has 4 generic I2C controller. This can support 17 master and slave mode of I2C communication. The i2c-tegra driver 18 only support master mode of I2C communication. Driver of I2C [all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra114.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra114-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra114-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 10 compatible = "nvidia,tegra114"; 11 interrupt-parent = <&lic>; 12 #address-cells = <1>; [all …]
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| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/reset/tegra124-car.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 13 interrupt-parent = <&lic>; [all …]
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| D | tegra114-tn7.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include "tegra114.dtsi" 9 compatible = "nvidia,tn7", "nvidia,tegra114"; 15 linux,initrd-start = <0x82000000>; 16 linux,initrd-end = <0x82800000>; 24 trusted-foundations { 25 compatible = "tlm,trusted-foundations"; 26 tlm,version-major = <2>; [all …]
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| D | tegra114-dalmore.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 9 #include <dt-bindings/input/input.h> 10 #include "tegra114.dtsi" 13 model = "NVIDIA Tegra114 Dalmore evaluation board"; 14 compatible = "nvidia,dalmore", "nvidia,tegra114"; 17 rtc0 = "/i2c@7000d000/tps65913@58"; 23 stdout-path = "serial0:115200n8"; 34 hdmi-supply = <&vdd_5v0_hdmi>; 35 vdd-supply = <&vdd_hdmi_reg>; [all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/ |
| D | tegra114.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra114-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra114-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 10 compatible = "nvidia,tegra114"; 11 interrupt-parent = <&lic>; 12 #address-cells = <1>; [all …]
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| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/reset/tegra124-car.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 11 #include "tegra124-peripherals-opp.dtsi" [all …]
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| D | tegra114-asus-tf701t.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 /dts-v1/; 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 8 #include "tegra114.dtsi" 12 compatible = "asus,tf701t", "nvidia,tegra114"; 13 chassis-type = "convertible"; 29 trusted-foundations { 30 compatible = "tlm,trusted-foundations"; 31 tlm,version-major = <2>; [all …]
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| D | tegra114-tn7.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include "tegra114.dtsi" 9 compatible = "nvidia,tn7", "nvidia,tegra114"; 15 linux,initrd-start = <0x82000000>; 16 linux,initrd-end = <0x82800000>; 24 trusted-foundations { 25 compatible = "tlm,trusted-foundations"; 26 tlm,version-major = <2>; [all …]
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| D | tegra114-dalmore.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 9 #include <dt-bindings/input/input.h> 10 #include "tegra114.dtsi" 13 model = "NVIDIA Tegra114 Dalmore evaluation board"; 14 compatible = "nvidia,dalmore", "nvidia,tegra114"; 17 rtc0 = "/i2c@7000d000/tps65913@58"; 23 stdout-path = "serial0:115200n8"; 34 hdmi-supply = <&vdd_5v0_hdmi>; 35 vdd-supply = <&vdd_hdmi_reg>; [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 16 - nvidia,tegra20-pmc 17 - nvidia,tegra20-pmc 18 - nvidia,tegra30-pmc 19 - nvidia,tegra114-pmc [all …]
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| D | nvidia,nvec.txt | 4 - compatible : should be "nvidia,nvec". 5 - reg : the iomem of the i2c slave controller 6 - interrupts : the interrupt line of the i2c slave controller 7 - clock-frequency : the frequency of the i2c bus 8 - gpios : the gpio used for ec request 9 - slave-addr: the i2c address of the slave controller 10 - clocks : Must contain an entry for each entry in clock-names. 11 See ../clocks/clock-bindings.txt for details. 12 - clock-names : Must include the following entries: 14 - div-clk [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 16 - nvidia,tegra20-pmc 17 - nvidia,tegra30-pmc 18 - nvidia,tegra114-pmc 19 - nvidia,tegra124-pmc [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 13 interrupt-parent = <&lic>; [all …]
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| D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra210-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra210-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/reset/tegra210-car.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/tegra124-soctherm.h> 10 #include <dt-bindings/soc/tegra-pmc.h> [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 16 - enum: 17 - nvidia,tegra20-dsi 18 - nvidia,tegra30-dsi 19 - nvidia,tegra114-dsi [all …]
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| D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^dc@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-dc 21 - nvidia,tegra30-dc [all …]
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| D | nvidia,tegra20-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^hdmi@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-hdmi 21 - nvidia,tegra30-hdmi [all …]
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| D | nvidia,tegra20-vi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^vi@[0-9a-f]+$" 19 - const: nvidia,tegra20-vi 20 - const: nvidia,tegra30-vi 21 - const: nvidia,tegra114-vi [all …]
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| D | nvidia,tegra20-host1x.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The host1x top-level node defines a number of children, each 19 - enum: 20 - nvidia,tegra20-host1x 21 - nvidia,tegra30-host1x [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 11 #include "tegra132-peripherals-opp.dtsi" [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x" 5 - reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10 - interrupts: The interrupt outputs from the controller. 11 - #address-cells: The number of cells used to represent physical base addresses 13 - #size-cells: The number of cells used to represent the size of an address 15 - ranges: The mapping of the host1x address space to the CPU address space. [all …]
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| /kernel/linux/linux-5.10/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 4 # 32-bit ARM SoCs 39 bool "Enable support for Tegra114 family" 63 # 64-bit ARM SoCs 75 Tegra124's "4+1" Cortex-A15 CPU complex. 85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 88 and providing 256 CUDA cores. It supports hardware-accelerated en- 93 controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to 105 combination of Denver and Cortex-A57 CPU cores and a GPU based on 106 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU [all …]
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| /kernel/linux/linux-6.6/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 4 # 32-bit ARM SoCs 39 bool "Enable support for Tegra114 family" 63 # 64-bit ARM SoCs 75 Tegra124's "4+1" Cortex-A15 CPU complex. 85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 88 and providing 256 CUDA cores. It supports hardware-accelerated en- 93 controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to 106 combination of Denver and Cortex-A57 CPU cores and a GPU based on 107 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU [all …]
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